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ps022827-1212 product specification high-performance 8-b it microcontrollers z8 encore! xp ? f082a series copyright ?2012 zilog ? , inc. all rights reserved. www.zilog.com
ps022827-1212 p r e l i m i n a r y disclaimer z8 encore! xp ? f082a series product specification ii do not use this product in life support systems. life support policy zilog's products are not authorized for use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) are intended for surgical impl ant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a signi ficant injury to the user. a criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support devi ce or system or to affect its safety or effectiveness. document disclaimer ?2012 zilog, inc. all rights reserved . information in this pu blication concerning the devices, applications, or technology described is intend ed to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained w ithin this document has been verified according to the general principles of electrical and mechanical engineering. z8, z8 encore! and z8 encore! xp are trademarks or registered trademarks of zilog, inc. all other product or service names are the property of their respective owners. warning:
ps022827-1212 p r e l i m i n a r y revision history z8 encore! xp ? f082a series product specification iii revision history each instance in this document?s revision history reflects a change from its previous edi- tion. for more details, refer to the corresponding page(s) or appropriate links furnished in the table below. date revision level chapter/section description page no. dec 2012 27 port alternate function map- ping (non 8-pin parts), port alternate function mapping (8- pin parts) added missing port d data to table 15; cor- rected active low status (set overlines) for pa0 (t0out ), pa2 (reset ) and pa5 (t1out ) in table 16. 40 , 43 sep 2011 26 led drive enable register clarified statement surrounding the alternate function register as it relates to the led function; revised flash sector protect regis- ter description; revised packaging chapter. 53 , 157 , 245 sep 2008 25 overview, address space, register map, general-pur- pose input/output, available packages, ordering informa- tion added references to f042a series back in table 1, table 5, table 7 and table 14. 2 , 8 , 16 , 18 , 36 , 246 may 2008 24 overview, address space, register map, general-pur- pose input/output, available packages, ordering informa- tion changed title to z8 encore! xp f082a series and removed references to f042a series in table 1, table 5, table 7 and table 14. 2 , 8 , 16 , 18 , 36 , 246 dec 2007 23 pin description, general-pur- pose input/output, watchdog timer updated figure 3, table 15, tables 60 through 62. 9 , 40 , 97 jul 2007 22 electrical characteristics updated tables 16 and 132; power con- sumption data. 43 , 229 jun 2007 21 n/a revision number update. all
ps022827-1212 p r e l i m i n a r y table of contents z8 encore! xp ? f082a series product specification iv table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 low-power operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 external crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 low voltage detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 direct led drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 non-volatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ps022827-1212 p r e l i m i n a r y table of contents z8 encore! xp ? f082a series product specification v reset, stop mode recovery and low voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 voltage brown-out reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 external reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 external reset indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 on-chip debugger initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 stop mode recovery using watchdog timer time-o ut . . . . . . . . . . . . . . . . . . . . . 28 stop mode recovery using a gpio port pin transition . . . . . . . . . . . . . . . . . . . . . 28 stop mode recovery usin g the external reset pin . . . . . . . . . . . . . . . . . . . . . . . 29 low voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 reset register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 peripheral-level power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 power control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 direct led drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 shared reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 shared debug pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 crystal oscillator override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 v tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 external clock setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 port a?d address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 port a?d control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 port a?d data direction subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 port a?d alternate function subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 port a?c input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 port a?d output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 led drive enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 led drive level high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ps022827-1212 p r e l i m i n a r y table of contents z8 encore! xp ? f082a series product specification vi led drive level low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 gpio mode interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 watchdog timer interrupt as sertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 shared interrupt select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 timer pin signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 timer 0?1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 timer 0?1 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 timer 0?1 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 watchdog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 watchdog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 watchdog timer reload unlo ck sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 watchdog timer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 watchdog timer control register defi nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 watchdog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 watchdog timer reload upper, high and low by te registers . . . . . . . . . . . . . . . 97
ps022827-1212 p r e l i m i n a r y table of contents z8 encore! xp ? f082a series product specification vii universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 transmitting data using the interrupt-driven method . . . . . . . . . . . . . . . . . . . . . . 102 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 receiving data using the interrupt -driven method . . . . . . . . . . . . . . . . . . . . . . . . 104 clear to send (cts) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 uart control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 uart status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 uart receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 uart baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . 117 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 20 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 infrared encoder/decoder control register definitions . . . . . . . . . . . . . . . . . . . . . . . . 123 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 hardware overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 automatic powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 calibration and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 adc compensation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 input buffer stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 adc control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 adc control/status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
ps022827-1212 p r e l i m i n a r y table of contents z8 encore! xp ? f082a series product specification viii adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 adc data low byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 low power operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 comparator control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 flash operation timing using the flash frequenc y registers . . . . . . . . . . . . . . . 149 flash code protection against external access . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 flash code protection against accidental prog ram and erasure . . . . . . . . . . . . . 149 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 flash option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 option bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 reading the flash information page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 flash option bit control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 trim bit address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 trim bit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 flash option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 flash program memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 flash program memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 trim bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
ps022827-1212 p r e l i m i n a r y table of contents z8 encore! xp ? f082a series product specification ix trim bit address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 trim bit address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 trim bit address 0002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 trim bit address 0003h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 trim bit address 0004h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 zilog calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 adc calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 temperature sensor calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 watchdog timer calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 serialization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 randomized lot identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 nonvolatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 nvds code interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 power failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 optimizing nvds memory usage for execution speed . . . . . . . . . . . . . . . . . . . . 178 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 ocd auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 ocd unlock sequence (8-pin devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 runtime counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 oscillator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 system clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 clock failure detection and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 oscillator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
ps022827-1212 p r e l i m i n a r y table of contents z8 encore! xp ? f082a series product specification x operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 oscillator operation with an external rc network . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 233 general purpose i/o port input da ta sample timing . . . . . . . . . . . . . . . . . . . . . . 240 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
ps022827-1212 p r e l i m i n a r y list of figures z8 encore! xp ? f082a series product specification xi list of figures figure 1. z8 encore! xp f082a series block diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. z8f08xa, z8f04xa, z8f02xa a nd z8f01xa in 8-pin soic, qfn/mlf-s, ? or pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. z8f08xa, z8f04xa, z8f02x a and z8f01xa in 20-pin soic, ssop ? or pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. z8f08xa, z8f04xa, z8f02x a and z8f01xa in 28-pin soic, ssop ? or pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. power-on reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. voltage brown-out reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. gpio port pin block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8. interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 9. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 10. uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 11. uart asynchronous data format withou t parity . . . . . . . . . . . . . . . . . . 101 figure 12. uart asynchronous data format with pa rity . . . . . . . . . . . . . . . . . . . . . 101 figure 13. uart asynchronous multiprocess or mode data format . . . . . . 105 figure 14. uart driver enable signal timing (shown with 1 stop bit and parity) 107 figure 15. uart receiver interrupt service routine flow . . . . . . . . . . . . . . . . . . . 109 figure 16. infrared data communi cation system block diagram . . . . . . . . . . . . . . 120 figure 17. infrared data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 18. irda data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 19. analog-to-digital conver ter block diagram . . . . . . . . . . . . . . . . . . . . . . 125 figure 20. comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 21. flash memory arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 22. flash controller operation flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 23. on-chip debugger block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 24. interfacing the on-chip debugg er?s dbg pin with an rs-232 interface; ? #1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
ps022827-1212 p r e l i m i n a r y list of figures z8 encore! xp ? f082a series product specification xii figure 25. interfacing the on-chip debugg er?s dbg pin with an rs-232 interface; ? #2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 26. ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 27. recommended 20 mhz crystal oscillato r configuration . . . . . . . . . . . . . 199 figure 28. connecting the on-chip oscillator to an external rc network . . . . . . . . 201 figure 29. typical rc oscillator frequency as a function of the ex ternal capacitance ? with a 45 k ? resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 30. opcode map cell description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 31. first opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 figure 32. second opcode map after 1fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 33. typical active mode idd versus sy stem clock frequency . . . . . . . . . . 231 figure 34. port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 figure 35. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 figure 36. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 figure 37. uart timing with cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 figure 38. uart timing without cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
ps022827-1212 p r e l i m i n a r y list of tables z8 encore! xp ? f082a series product specification xiii list of tables table 1. z8 encore! xp f082a series family part selection guide . . . . . . . . . . . . . 2 table 2. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. pin characteristics (20- and 28-pin devices) . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. pin characteristics (8-pin devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. z8 encore! xp f082a series program me mory maps . . . . . . . . . . . . . . . . 16 table 6. z8 encore! xp f082a series flash memory information area map . . . . . 17 table 7. register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. reset and stop mode recovery character istics and latency . . . . . . . . . . . 23 table 9. reset sources and resulting reset type . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. stop mode recovery so urces and resulting action . . . . . . . . . . . . . . . . . . 28 table 11. reset status register (rststat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. reset and stop mode recovery bit descriptions . . . . . . . . . . . . . . . . . . . . 31 table 13. power control register 0 (pwrctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. port availability by device and package type . . . . . . . . . . . . . . . . . . . . . . 36 table 15. port alternate function mapping (non 8-pi n parts) . . . . . . . . . . . . . . . . . . 40 table 16. port alternate function mapping (8-pin parts) . . . . . . . . . . . . . . . . . . . . . . 43 table 17. gpio port registers and subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 18. port a?d gpio address registers (pxaddr) . . . . . . . . . . . . . . . . . . . . . 45 table 19. port a?d gpio address registers by bit description . . . . . . . . . . . . . . . . 45 table 20. port a?d control registers (pxctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 21. port a?d data direction subregisters (px dd) . . . . . . . . . . . . . . . . . . . . . . 46 table 22. port a?d alternate functio n subregisters (pxaf) . . . . . . . . . . . . . . . . . . . 47 table 23. port a?d output control subregisters (pxoc) . . . . . . . . . . . . . . . . . . . . . 48 table 24. port a?d high drive enable subregisters (pxhde) . . . . . . . . . . . . . . . . . 48 table 25. port a?d stop mode recovery source enable subregisters (pxsmre) . . 49 table 26. port a?d pull-up enable subregisters (pxpue) . . . . . . . . . . . . . . . . . . . . 50 table 27. port a?d alternate function set 2 subreg isters (pxafs2) . . . . . . . . . . . . 51 table 28. port a?d alternate function set 1 subreg isters (pxafs1) . . . . . . . . . . . . 51
ps022827-1212 p r e l i m i n a r y list of tables z8 encore! xp ? f082a series product specification xiv table 29. port a?c input data registers (pxin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 30. port a?d output data register (pxout) . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 31. led drive enable (leden) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 32. led drive level high register (ledlvlh ) . . . . . . . . . . . . . . . . . . . . . . 53 table 33. led drive level low register (ledlvll) . . . . . . . . . . . . . . . . . . . . . . . 54 table 34. trap and interrupt vectors in order of prio rity . . . . . . . . . . . . . . . . . . . . . . 56 table 35. interrupt request 0 register (irq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 36. interrupt request 1 register (irq1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 37. interrupt request 2 register (irq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 38. irq0 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 39. irq0 enable high bit register (irq0enh) . . . . . . . . . . . . . . . . . . . . . . . 63 table 40. irq0 enable low bit register (irq0enl) . . . . . . . . . . . . . . . . . . . . . . . . 63 table 41. irq1 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 42. irq1 enable low bit register (irq1enl) . . . . . . . . . . . . . . . . . . . . . . . . 65 table 43. irq1 enable high bit register (irq1enh) . . . . . . . . . . . . . . . . . . . . . . . 65 table 44. irq2 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 45. irq2 enable high bit register (irq2enh) . . . . . . . . . . . . . . . . . . . . . . . 66 table 46. interrupt edge select register (irqes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 47. irq2 enable low bit register (irq2enl) . . . . . . . . . . . . . . . . . . . . . . . . 67 table 48. shared interrupt select register (irqss) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 49. interrupt control register (irqctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 50. timer 0?1 control register 0 (txctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 51. timer 0?1 control register 1 (txctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 52. timer 0?1 high byte register (txh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 53. timer 0?1 low byte register (txl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 54. timer 0?1 reload high byte register (t xrh) . . . . . . . . . . . . . . . . . . . . . . 91 table 55. timer 0?1 reload low byte register (txr l) . . . . . . . . . . . . . . . . . . . . . . 91 table 56. timer 0?1 pwm high byte register (txpwmh) . . . . . . . . . . . . . . . . . . . 92 table 57. timer 0?1 pwm low byte register (txpwml) . . . . . . . . . . . . . . . . . . . . 92 table 58. watchdog timer approximate time-out de lays . . . . . . . . . . . . . . . . . . . . 93
ps022827-1212 p r e l i m i n a r y list of tables z8 encore! xp ? f082a series product specification xv table 59. watchdog timer control register (wdtctl) . . . . . . . . . . . . . . . . . . . . . 96 table 60. watchdog timer reload upper byte register (wdtu) . . . . . . . . . . . . . . 97 table 61. watchdog timer reload high byte regi ster (wdth) . . . . . . . . . . . . . . . 97 table 62. watchdog timer reload low byte regist er (wdtl) . . . . . . . . . . . . . . . . 98 table 63. uart control 0 register (u0ctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 64. uart control 1 register (u0ctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 65. uart status 0 register (u0stat0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 66. uart status 1 register (u0stat1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 67. uart transmit data register (u0txd) . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 68. uart receive data register (u0rxd) . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 69. uart address compare register (u0addr) . . . . . . . . . . . . . . . . . . . . . 117 table 70. uart baud rate high byte register (u0brh) . . . . . . . . . . . . . . . . . . . 117 table 71. uart baud rate low byte register (u0brl) . . . . . . . . . . . . . . . . . . . . 117 table 72. uart baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 73. adc control register 0 (adcctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 74. adc control/status register 1 (adcctl1) . . . . . . . . . . . . . . . . . . . . . . 136 table 75. adc data high byte register (adcd_h) . . . . . . . . . . . . . . . . . . . . . . . . 137 table 76. adc data low byte register (adcd_l) . . . . . . . . . . . . . . . . . . . . . . . . 137 table 77. comparator control register (cmp0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 78. z8 encore! xp f082a series flash me mory configurations . . . . . . . . . . 146 table 79. flash code protection using the flash op tion bits . . . . . . . . . . . . . . . . . 150 table 80. flash status register (fstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 81. flash control register (fctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 82. flash page select register (fps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 83. flash sector protect register (fprot) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 84. flash frequency high byte register ( ffreqh) . . . . . . . . . . . . . . . . . . . 158 table 85. flash frequency low byte register (ffr eql) . . . . . . . . . . . . . . . . . . . . 158 table 86. trim bit address register (trmadr) . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 87. trim bit data register (trmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 88. flash option bits at program memory address 0000h . . . . . . . . . . . . . . 162
ps022827-1212 p r e l i m i n a r y list of tables z8 encore! xp ? f082a series product specification xvi table 89. flash options bits at program memory address 0001h . . . . . . . . . . . . . 164 table 90. trim options bits at address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 91. trim option bits at 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 92. trim option bits at 0002h (tipo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 93. trim option bits at address 0003h (tlvd) . . . . . . . . . . . . . . . . . . . . . . 166 table 94. lvd trim values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 95. trim option bits at 0004h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 96. adc calibration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 97. adc calibration data location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 98. temperature sensor calibration high byte at 003a (tscalh) . . . . . . . 171 table 99. temperature sensor calibration low byte at 003b (tscall) . . . . . . . . 171 table 100. watchdog calibration high byte at 007eh (wdtcalh) . . . . . . . . . . . . 172 table 101. serial number at 001c - 001f (s_num) . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 102. serialization data locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 103. watchdog calibration low byte at 007fh (wdtcall) . . . . . . . . . . . . 173 table 104. lot identification number (rand_lot) . . . . . . . . . . . . . . . . . . . . . . . . 174 table 105. randomized lot id locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 106. write status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 107. nvds read time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 108. ocd baud-rate limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 109. debug command enable/disab le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 110. ocd control register (ocdctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 111. ocd status register (ocdstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 112. oscillator configuration and selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 113. oscillator control register (oscctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 114. recommended crystal oscillator specific ations . . . . . . . . . . . . . . . . . . . 200 table 115. transconductance values for low, medium and high gain operating ? modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 116. assembly language syntax example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 117. assembly language syntax example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 118. notational shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
ps022827-1212 p r e l i m i n a r y list of tables z8 encore! xp ? f082a series product specification xvii table 119. additional symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 120. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 121. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 122. block transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 123. cpu control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 124. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 125. logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 126. program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 127. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 128. ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 129. opcode map abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 130. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 131. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 132. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 133. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 134. internal precision oscillator electrical characteristics . . . . . . . . . . . . . . . 232 table 135. power-on reset and voltage br own-out electrical characteristics ? and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 136. flash memory electrical characteristic s and timing . . . . . . . . . . . . . . . . 234 table 137. watchdog timer electrical characteri stics and timing . . . . . . . . . . . . . . 235 table 138. non-volatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 139. analog-to-digital converter electrical characteristics and timing . . . . . 236 table 140. low power operational amplifier elec trical characteristics . . . . . . . . . . 238 table 141. comparator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 142. temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . 239 table 143. gpio port input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 144. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 145. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 146. uart timing with cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 147. uart timing without cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table 148. z8 encore! xp f082a series ordering ma trix . . . . . . . . . . . . . . . . . . . . . 246
ps022827-1212 p r e l i m i n a r y overview z8 encore! xp ? f082a series product specification 1 overview zilog?s z8 encore! mcu family of products ar e the first in a line of zilog microcontroller products based upon the 8-bit ez8 cpu. zilog?s z8 encore! xp f082a series products expand upon zilog?s extensive line of 8-bit microcontrollers. the flash in-circuit pro- gramming capability allows for faster develo pment time and program ch anges in the field. the new ez8 cpu is upward compatible with ex isting z8 instructions. the rich peripheral set of the z8 encore! xp f082a series makes it suitable for a variety of applications including motor control, secur ity systems, home appliances, personal electronic devices and sensors. features the key features of z8 encore! xp f082a series products include: ? 20 mhz ez8 cpu ? 1 kb, 2 kb, 4 kb, or 8 kb flash memory with in-circuit programming capability ? 256 b, 512 b, or 1 kb register ram ? up to 128 b nonvolatile data storage (nvds) ? internal precision oscillato r trimmed to 1% accuracy ? external crystal oscillator, operating up to 20 mhz ? optional 8-channel, 10-bit analog-to-digital converter (adc) ? optional on-chip temperature sensor ? on-chip analog comparator ? optional on-chip low-power operational amplifier (lpo) ? full-duplex uart ? the uart baud rate generator (brg) can be configured and used as a basic 16-bit timer ? infrared data association (irda)-compliant infrared encoder/decoders, integrated with the uart ? two enhanced 16-bit timers with capture, compare and pwm capability ? watchdog timer (wdt) with de dicated internal rc oscillator ? up to 20 vectored interrupts ? 6 to 25 i/o pins depending upon package ? up to thirteen 5 v-tolerant input pins
ps022827-1212 p r e l i m i n a r y part selection guide z8 encore! xp ? f082a series product specification 2 ? up to 8 ports capable of direct led driv e with no current limit resistor required ? on-chip debugger (ocd) ? voltage brown-out (vbo) protection ? programmable low battery detec tion (lvd) (8-pin devices only) ? bandgap generated precision voltage refe rences available for the adc, comparator, vbo and lvd ? power-on reset (por) ? 2.7 v to 3.6 v operating voltage ? 8-, 20- and 28-pin packages ? 0c to +70c and ?40c to +105c for operating temperature ranges part selection guide table 1 identifies the basic features and package styles available for each device within the z8 encore! xp f082a series product line. table 1. z8 encore! xp f082a series family part selection guide part number flash (kb) ram (b) nvds 1 (b) i/o comparator advanced analog 2 adc inputs packages z8f082a 8 1024 0 6?23 yes yes 4?8 8-, 20- and 28-pin z8f081a 8 1024 0 6?25 yes no 0 8-, 20- and 28-pin z8f042a 4 1024 128 6?23 yes yes 4?8 8-, 20- and 28-pin z8f041a 4 1024 128 6?25 yes no 0 8-, 20- and 28-pin z8f022a 2 512 64 6?23 yes yes 4?8 8-, 20- and 28-pin z8f021a 2 512 64 6?25 yes no 0 8-, 20- and 28-pin z8f012a 1 256 16 6?23 yes yes 4?8 8-, 20- and 28-pin z8f011a 1 256 16 6?25 yes no 0 8-, 20- and 28-pin notes: 1. non-volatile data storage. 2. advanced analog includes adc, temperatur e sensor and low-power operational amplifier.
ps022827-1212 p r e l i m i n a r y block diagram z8 encore! xp ? f082a series product specification 3 block diagram figure 1 displays the block diagram of th e architecture of the z8 encore! xp f082a series devices. figure 1. z8 encore! xp f082a series block diagram gpio irda uart timers adc flash memory flash controller ram ram controller interrupt controller on-chip debugger ez8 cpu wdt por/vbo and reset controller xtal/rc oscillator register bus memory busses system clock comparator temperature sensor nvds controller low power rc oscillator internal oscillator control oscillator precision low power op amp
ps022827-1212 p r e l i m i n a r y cpu and peripheral overview z8 encore! xp ? f082a series product specification 4 cpu and peripheral overview the ez8 cpu, zilog?s latest 8-bit central processing unit (cpu), meets the continuing demand for faster and more code-efficient microcontrollers. the ez8 cpu executes a superset of the original z8 instruction set. the features of ez8 cpu include: ? direct register-to-register architecture allows each register to function as an accumulator, improving exec ution time and decreasing the required program memory ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks ? compatible with existing z8 code ? expanded internal register file allows access of up to 4 kb ? new instructions improve execution effici ency for code developed using higher- level programming languages, including c ? pipelined instruction fetch and execution ? new instructions for improved performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult and srl ? new instructions support 12-bit linea r addressing of the register file ? up to 10 mips operation ? c-compiler friendly ? 2 to 9 clock cycles per instruction ? for more information abou t ez8 cpu, refer to the ez8 cpu core user manual (um0128) , which is available for download on www.zilog.com . 10-bit analog-to- digital converter the optional analog-to-digital co nverter (adc) converts an analog input signal to a 10-bit binary number. the adc accepts inputs from eigh t different analog input pins in both sin- gle-ended and differential modes. the adc also features a unity gain buffer when high input impedance is required. low-power operational amplifier the optional low-power operatio nal amplifier (lpo) is a ge neral-purpose amplifier pri- marily targeted for current sense applications. the lpo output may be routed internally to the adc or externally to a pin.
ps022827-1212 p r e l i m i n a r y cpu and peripheral overview z8 encore! xp ? f082a series product specification 5 internal precision oscillator the internal precision oscillator (ipo) is a tr immable clock source that requires no exter- nal components. temperature sensor the optional temperature sensor produces an anal og output proportional to the device tem- perature. this signal can be sent to e ither the adc or the analog comparator. analog comparator the analog comparator compares the signal at an input pin with either an internal pro- grammable voltage reference or a second input pin. the comparat or output can be used to drive either an output pin or to generate an interrupt. external crystal oscillator the crystal oscillator circuit pr ovides highly accurate clock fre quencies with the use of an external crystal, ceramic resonator or rc network. low voltage detector the low voltage detector (lvd) is able to ge nerate an interrupt wh en the supply voltage drops below a user-programmable level. th e lvd is available on 8-pin devices only. on-chip debugger the z8 encore! xp f082a series products feature an integrated on-chip debugger (ocd) accessed via a single-pin inte rface. the ocd provides a rich- set of debugging capabilities, such as reading and writing registers, progr amming flash memory, setting breakpoints and executing code. universal asynchronous receiver/transmitter the full-duplex universal asynchronous receiver /transmitter (uart) is included in all z8 encore! xp package types. the uart supports 8- and 9-bit data modes and selectable parity. the uart also supports multi-drop address processing in hardware. the uart baud rate generator (brg) can be config ured and used as a basic 16-bit timer. timers two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provid e a 16-bit programmable reload counter and
ps022827-1212 p r e l i m i n a r y cpu and peripheral overview z8 encore! xp ? f082a series product specification 6 operate in one-shot, continuous, gated, capture, capture restart, compare, capture and compare, pwm single output and pwm dual output modes. general-purpose input/output the product line mcus feature 6 to 25 port pins (ports a?d) for general- purpose input/ output (gpio). the number of gpio pins available is a function of package and each pin is individually programmable. 5 v tole rant input pins are available on all ? i/os on 8-pin devices and most i/os on other package types. direct led drive the 20- and 28-pin devices support controlled current sinking output pins capable of driv- ing leds without the need for a current limiting resi stor. these led drivers are indepen- dently programmable to four different intensity levels. flash controller the flash controller programs and erases fl ash memory. the flash controller supports several protection mechanisms against accidental program and erasure, plus factory serial- ization and read protection. non-volatile data storage the nonvolatile data storage (nvds) uses a hy brid hardware/softwar e scheme to imple- ment a byte programmable data memory and is capable of over 100,000 write cycles. devices with 8 kb of flash memory do not include the nvds feature. interrupt controller the z8 encore! xp f082a series products support up to 20 interrupts. these interrupts consist of 8 internal peripheral interrupts and 12 general-purpose i/o pin interrupt sources. the interrupts have three levels of programmable interrupt priority. reset controller the z8 encore! xp f082a series pr oducts can be reset using the reset pin, power-on reset, watchdog timer (wdt) time-out, stop mode exit, or voltage brown-out (vbo) note:
ps022827-1212 p r e l i m i n a r y cpu and peripheral overview z8 encore! xp ? f082a series product specification 7 warning signal. the reset pin is bidirectional, that is, it functions as reset source and as a reset indicator.
ps022827-1212 p r e l i m i n a r y pin description z8 encore! xp ? f082a series product specification 8 pin description the z8 encore! xp f082a series products ar e available in a variety of packages styles and pin configurations. this ch apter describes the signals and available pin configurations for each of the package styles. for informatio n about physical package specifications, see the packaging chapter on page 245. available packages the following package styles are available fo r each device in the z8 encore! xp f082a series product line: ? soic: 8-, 20- and 28-pin ? pdip: 8-, 20- and 28-pin ? ssop: 20- and 28- pin ? qfn 8-pin (mlf-s, a qfn-style packag e with an 8-pin soic footprint) ? in addition, the z8 encore! xp f082a series devices are ava ilable both with and without advanced analog capability ( adc, temperature sensor and op amp). devices z8f082a, z8f042a, z8f022a and z8f012a contain the advanced analog, while devices z8f081a, z8f041a, z8f021a and z8f011a do not have the advanced analog capability. pin configurations figure 2 through figure 4 display the pin conf igurations for all the packages available in the z8 encore! xp f082a series. see table 2 on page 10 for a description of the signals. the analog input alternate functions (ana x ) are not available on the z8f081a, z8f041a, z8f021a and z8f011a devices. the analog supply pins (av dd and av ss ) are also not available on these parts and are replaced by pb6 and pb7. at reset, all port a, b and c pins default to an input state. in add ition, any alternate func- tionality is not enabled, so the pins function as general purpose input ports until pro- grammed otherwise. at powerup, the pd0 pin defaults to the reset alternate function. the pin configurations listed are preliminary and subject to change based on manufactur- ing limitations.
ps022827-1212 p r e l i m i n a r y pin configurations z8 encore! xp ? f082a series product specification 9 figure 2. z8f08xa, z8f04xa, z8f02xa and z8f01x a in 8-pin soic, qfn/mlf-s, or pdip package figure 3. z8f08xa, z8f04xa, z8f02xa and z8f01xa in 20-pin soic, ssop or pdip package figure 4. z8f08xa, z8f04xa, z8f02xa and z8f01xa in 28-pin soic, ssop or pdip package vss pa5/txd0/t1out /ana0/cinp/ampout pa4/rxd0/ana1/cinn/ampinn pa3/cts0 /ana2/cout/ampinp/t1in vdd pa0/t0in/t0out /xin//dbg pa1/t0out/x out /ana3/vref/clkin pa2/reset /de0/t1out 2 1 3 4 7 8 6 5 pb0/ana0/ampout pc3/cout/led pc2/ana6/led/vref pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset /pd0 pa7/t1out pa6/t1in/t1out pb1/ana1/ampinn pb2/ana2/ampinp pb3/clkin/ana3 vdd pa0/t0in/t0out /xin pa1/t0out/x out vss pa2/de0 1 pa5/txd0 pa3/cts0 5 10 pa4/rxd0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb1/ana1/ampinn pb0/ana0/ampout pc3/cout/led pc2/ana6/led pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset /pd0 pc7/led pb2/ana2/ampinp pb3/clkin/ana3 pb4/ana7 pb5/vref (pb6) avdd vdd pa0/t0in/t0out /xin pa1/t0out/x out 1 pc6/led vss 5 10 (pb7) avss pa2/de0 pa3/cts0 pa4/rxd0 14 pa5/txd0 2 3 4 6 7 8 9 11 12 13 pc5/led pc4/led pa7/t1out pa6/t1in/t1out 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps022827-1212 p r e l i m i n a r y signal descriptions z8 encore! xp ? f082a series product specification 10 signal descriptions table 2 describes the z8 encore! xp f082a series signals. see the pin configurations section on page 8 to determine the signal s available for the sp ecific package styles. table 2. signal descriptions signal mnemonic i/o description general-purpose i/o ports a?d pa[7:0] i/o port a. these pins are used for general-purpose i/o. pb[7:0] i/o port b. these pins are used for general-purpose i/o. pb6 and pb7 are available only in those devices without an adc. pc[7:0] i/o port c. these pins are used for general-purpose i/o. pd[0] i/o port d. this pin is used for general-purpose output only. uart controllers txd0 o transmit data. this signal is the transmit output from the uart and irda. rxd0 i receive data. this signal is th e receive input for the uart and irda. cts0 i clear to send. this signal is th e flow control input for the uart. de o driver enable. this signal allows au tomatic control of external rs-485 drivers. this signal is approximat ely the inverse of the txe (transmit empty) bit in the uart status 0 re gister. the de signal may be used to ensure the external rs-485 driver is enabled when data is transmitted by the uart. timers t0out/t1out o timer output 0?1. these signals are outputs from the timers. t0out /t1out o timer complement output 0?1. these signals are output from the timers in pwm dual output mode. t0in/t1in i timer input 0?1. these signals are used as the capture, gating and coun- ter inputs. comparator cinp/cinn i comparator inputs. these signals are the positive and negative inputs to the comparator. cout o comparator output. notes: 1. pb6 and pb7 are only available in 28-pin packages wi thout adc. in 28-pin packages with adc, they are replaced by av dd and av ss . 2. the av dd and av ss signals are available only in 28-pin packages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc.
ps022827-1212 p r e l i m i n a r y signal descriptions z8 encore! xp ? f082a series product specification 11 analog ana[7:0] i analog port. these signals are used as inputs to the analog-to-digital con- verter (adc). vref i/o analog-to-digital converter reference voltage input, or buffered output for internal reference. low-power operationa l amplifier (lpo) ampinp/ampinn i lpo inputs. if enabled, these pi ns drive the positive and negative amplifier inputs respectively. ampout o lpo output. if enabled, this pin is driven by the on-chip lpo. oscillators xin i external crystal input. th is is the input pin to the crystal oscillator. a crystal can be connected between it and the x out pin to form the oscillator. in addition, this pin is used with external rc networks or ex ternal clock driv- ers to provide the system clock. x out o external crystal output. this pin is th e output of the crystal oscillator. a crystal can be connected between it and the xin pin to form the oscillator. clock input clkin i clock input signal. this pin may be used to input a ttl-level signal to be used as the system clock. led drivers led o direct led drive capability. all port c pins have the capability to drive an led without any other external components. these pins have programma- ble drive strengths set by the gpio block. on-chip debugger dbg i/o debug. this signal is the control and data input and output to and from the on-chip debugger. ? caution: the dbg pin is open-drain and requires a pull-up resistor to ensure proper operation. table 2. signal descriptions (continued) signal mnemonic i/o description notes: 1. pb6 and pb7 are only available in 28-pin packages wi thout adc. in 28-pin packages with adc, they are replaced by av dd and av ss . 2. the av dd and av ss signals are available only in 28-pin packages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc.
ps022827-1212 p r e l i m i n a r y pin characteristics z8 encore! xp ? f082a series product specification 12 pin characteristics table 3 describes the characteri stics for each pin available on the z8 encore! xp f082a series 20- and 28-pin devices. data in table 3 is sorted alphabetically by the pin symbol mnemonic. table 4 on page 14 provides deta iled information about the ch aracteristics for each pin available on the z8 encore! xp f082a series 8-pin devices. all six i/o pins on the 8-pin packages are 5 v-tolerant (unless the pull-up devices are enabled). the column in table 3 below desc ribes 5 v-tolerance fo r the 20- and 28-pin packages only. reset reset i/o reset. generates a reset when assert ed (driven low). also serves as a reset indicator; the z8 en core! xp forces this pin lo w when in reset. this pin is open-drain and features an enabled internal pull-up resistor. power supply v dd i digital power supply. av dd i analog power supply. v ss i digital ground. av ss i analog ground. table 2. signal descriptions (continued) signal mnemonic i/o description notes: 1. pb6 and pb7 are only available in 28-pin packages wi thout adc. in 28-pin packages with adc, they are replaced by av dd and av ss . 2. the av dd and av ss signals are available only in 28-pin packages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc. note:
ps022827-1212 p r e l i m i n a r y pin characteristics z8 encore! xp ? f082a series product specification 13 pb6 and pb7 are available only in those devices without adc. table 3. pin characteristics (20- and 28-pin devices) symbol ? mnemonic direction reset direction active low or active high tristate output internal pull-up or pull-down schmitt- trigger input open drain output 5 v tolerance avdd n/a n/a n/a n/a n/a n/a n/a n/a avss n/a n/a n/a n/a n/a n/a n/a na dbg i/o i n/a yes yes yes yes no pa[7:0] i/o i n/a yes programma- ble pull-up yes yes, programma- ble pa[7:2] unless pul- lups enabled pb[7:0] i/o i n/a yes programma- ble pull-up yes yes, programma- ble pb[7:6] unless pul- lups enabled pc[7:0] i/o i n/a yes programma- ble pull-up yes yes, programma- ble pc[7:3] unless pul- lups enabled reset/ pd0 i/o i/o (defaults to reset ) low (in reset mode) yes (pd0 only) programma- ble for pd0; always on for reset yes programma- ble for pd0; always on for reset yes, unless pul- lups enabled vdd n/a n/a n/a n/a n/a n/a vss n/a n/a n/a n/a n/a n/a note:
ps022827-1212 p r e l i m i n a r y pin characteristics z8 encore! xp ? f082a series product specification 14 ) table 4. pin characteristics (8-pin devices) symbol ? mnemonic direction reset direction active low or active high tristate output internal pull-up or pull-down schmitt- trigger input open drain output 5 v tolerance pa0/dbg i/o i (but can change during reset if key sequence detected) n/a yes programma- ble pull-up yes yes, programma- ble yes, unless pull-ups enabled pa1 i/o i n/a yes programma- ble pull-up yes yes, programma- ble yes, unless pull-ups enabled reset / pa2 i/o i/o (defaults to reset ) low (in reset mode) yes programma- ble for pa2; always on for reset yes programma- ble for pa2; always on for reset yes, unless pull-ups enabled pa[5:3] i/o i n/a yes programma- ble pull-up yes yes, programma- ble yes, unless pull-ups enabled v dd n/a n/a n/a n/a n/a n/a n/a n/a v ss n/a n/a n/a n/a n/a n/a n/a n/a
ps022827-1212 p r e l i m i n a r y address space z8 encore! xp ? f082a series product specification 15 address space the ez8 cpu can access the following three distinct address spaces: ? the register file contains addresses for the general-purpose registers and the ez8 cpu, peripheral and general-purp ose i/o port control registers. ? the program memory contains addresses for all memory locations having executable code and/or data. ? the data memory contains addresses for all memory locations that contain data only. ? these three address spaces are covered brie fly in the following subsections. for more information about ez8 cpu and its address space, refer to the ez8 cpu core user manual (um0128) , which is available for download on www.zilog.com . register file the register file address space in the z8 encore! mcu is 4 kb (4096 bytes). the regis- ter file is composed of two sections: control registers and general-purpose registers. when instructions are executed, registers defined as sources are read and registers defined as destinations are written. the architecture of the ez8 cpu allows all general-purpose regis- ters to function as accumulators, address pointe rs, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 4 kb register file address space are reserved for control of the ez8 cpu, the on-chip peripherals and the i/ o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256 b control register section are reserved (unavailable). reading fro m a reserved register file address returns an undefined value. writing to reserved register file addr esses is not recommended and can produce unpredictable results. the on-chip ram always begins at address 000h in the register file address space. the z8 encore! xp ? f082a series devices contain 256 b to 1 kb of on-chip ram. reading from register file addresses outside the availa ble ram addresses (and not within the con- trol register address space) returns an unde fined value. writing to these register file addresses produces no effect. program memory the ez8 cpu supports 64 kb of program memory address space. the z8 encore! xp f082a series devices contain 1 kb to 8 kb of on-chip flash memory in the program memory address space, depending on the device. reading from program memory
ps022827-1212 p r e l i m i n a r y program memory z8 encore! xp ? f082a series product specification 16 addresses outside the available flash memory addresses returns ffh . writing to these unimplemented program memory addresses prod uces no effect. table 5 describes the pro- gram memory maps for the z8 encore! xp f082a series products. table 5. z8 encore! xp f082a series program memory maps program memory address (hex) function z8f082a and z8f081a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?0039 reserved 003a?003d oscillator fail trap vectors 003e?1fff program memory z8f042a and z8f041a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?0039 reserved 003a?003d oscillator fail trap vectors 003e?0fff program memory z8f022a and z8f021a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?0039 reserved 003a?003d oscillator fail trap vectors 003e?07ff program memory z8f012a and z8f011a products 0000?0001 flash option bits note: *see table 32 on page 56 for a list of the interrupt vectors.
ps022827-1212 p r e l i m i n a r y data memory z8 encore! xp ? f082a series product specification 17 data memory the z8 encore! xp f082a series does not use the ez8 cpu?s 64 kb data memory address space. flash information area table 6 describes the z8 encore! xp f082a series flash information area. this 128 b information area is accessed by setting bit 7 of the flash page select register to 1. when access is enabled, the flash information area is mapped into the program memory and overlays the 128 bytes at addresses fe00h to ff7fh . when the information area access is enabled, all reads from these program memory addresses return the information area data rather than the program memory data. access to the flash informatio n area is read-only. 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?0039 reserved 003a?003d oscillator fail trap vectors 003e?03ff program memory table 6. z8 encore! xp f082a series flash memory information area map program memory address (hex) function fe00?fe3f zilog option bits/calibration data fe40?fe53 part number 20-character ascii alphanumeric code left-justified and filled with ffh fe54?fe5f reserved fe60?fe7f zilog calibration data fe80?ffff reserved table 5. z8 encore! xp f082a series program memory maps (continued) program memory address (hex) function note: *see table 32 on page 56 for a list of the interrupt vectors.
ps022827-1212 p r e l i m i n a r y register map z8 encore! xp ? f082a series product specification 18 register map table 7 provides the address map for the register file of the z8 encore! xp f082a series devices. not all devices and p ackage styles in the z8 enco re! xp f082a series support the adc, or all of the gpio ports. consider registers for unimplem ented peripherals as reserved. table 7. register file address map address (hex) register description mnemonic reset (hex) page general-purpose ram z8f082a/z8f081a devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f042a/z8f041a devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f022a/z8f021a devices 000?1ff general-purpose register file ram ? xx 200?eff reserved ? xx z8f012a/z8f011a devices 000?0ff general-purpose register file ram ? xx 100?eff reserved ? xx timer 0 f00 timer 0 high byte t0h 00 90 f01 timer 0 low byte t0l 01 90 f02 timer 0 reload high byte t0rh ff 91 f03 timer 0 reload low byte t0rl ff 91 f04 timer 0 pwm high byte t0pwmh 00 92 f05 timer 0 pwm low byte t0pwml 00 92 f06 timer 0 control 0 t0ctl0 00 85 f07 timer 0 control 1 t0ctl1 00 86 notes: 1. xx = undefined. 2. refer to the ez8 cpu core user manual (um0128) .
ps022827-1212 p r e l i m i n a r y register map z8 encore! xp ? f082a series product specification 19 timer 1 f08 timer 1 high byte t1h 00 90 f09 timer 1 low byte t1l 01 90 f0a timer 1 reload high byte t1rh ff 91 timer 1 (cont?d) f0b timer 1 reload low byte t1rl ff 91 f0c timer 1 pwm high byte t1pwmh 00 92 f0d timer 1 pwm low byte t1pwml 00 92 f0e timer 1 control 0 t1ctl0 00 85 f0f timer 1 control 1 t1ctl1 00 86 f10?f6f reserved ? xx uart f40 uart transmit/receive data registers txd, rxd xx 115 f41 uart status 0 register u0stat0 00 114 f42 uart control 0 register u0ctl0 00 110 f43 uart control 1 register u0ctl1 00 110 f44 uart status 1 register u0stat1 00 115 f45 uart address compare register u0addr 00 116 f46 uart baud rate high byte register u0brh ff 117 f47 uart baud rate low byte register u0brl ff 117 analog-to-digital converter (adc) f70 adc control 0 adcctl0 00 134 f71 adc control 1 adcctl1 80 136 f72 adc data high byte adcd_h xx 137 f73 adc data low byte adcd_l xx 137 f74?f7f reserved ? xx low power control f80 power control 0 pwrctl0 80 34 f81 reserved ? xx led controller f82 led drive enable leden 00 53 f83 led drive level high byte ledlvlh 00 53 f84 led drive level low byte ledlvll 00 54 table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page notes: 1. xx = undefined. 2. refer to the ez8 cpu core user manual (um0128) .
ps022827-1212 p r e l i m i n a r y register map z8 encore! xp ? f082a series product specification 20 f85 reserved ? xx oscillator control f86 oscillator control oscctl a0 196 f87?f8f reserved ? xx comparator 0 f90 comparator 0 control cmp0 14 141 f91?fbf reserved ? xx interrupt controller fc0 interrupt request 0 irq0 00 60 fc1 irq0 enable high bit irq0enh 00 63 fc2 irq0 enable low bit irq0enl 00 63 fc3 interrupt request 1 irq1 00 61 fc4 irq1 enable high bit irq1enh 00 65 fc5 irq1 enable low bit irq1enl 00 65 fc6 interrupt request 2 irq2 00 62 fc7 irq2 enable high bit irq2enh 00 66 fc8 irq2 enable low bit irq2enl 00 67 fc9?fcc reserved ? xx fcd interrupt edge select irqes 00 68 fce shared interrupt select irqss 00 68 fcf interrupt control irqctl 00 69 gpio port a fd0 port a address paaddr 00 44 fd1 port a control pactl 00 46 fd2 port a input data pain xx 46 fd3 port a output data paout 00 46 gpio port b fd4 port b address pbaddr 00 44 fd5 port b control pbctl 00 46 fd6 port b input data pbin xx 46 fd7 port b output data pbout 00 46 gpio port c fd8 port c address pcaddr 00 44 table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page notes: 1. xx = undefined. 2. refer to the ez8 cpu core user manual (um0128) .
ps022827-1212 p r e l i m i n a r y register map z8 encore! xp ? f082a series product specification 21 fd9 port c control pcctl 00 46 fda port c input data pcin xx 46 fdb port c output data pcout 00 46 gpio port d fdc port d address pdaddr 00 44 fdd port d control pdctl 00 46 fde reserved ? xx fdf port d output data pdout 00 46 fe0?fef reserved ? xx watchdog timer (wdt) ff0 reset status (read-only) rststat x0 29 watchdog timer control (write-only) wdtctl n/a 96 ff1 watchdog timer reload upper byte wdtu 00 97 ff2 watchdog timer reload high byte wdth 04 97 ff3 watchdog timer reload low byte wdtl 00 98 ff4?ff5 reserved ? xx trim bit control ff6 trim bit address trmadr 00 161 ff7 trim bit data trmdr 00 162 flash memory controller ff8 flash control fctl 00 155 ff8 flash status fstat 00 155 ff9 flash page select fps 00 156 flash sector protect fprot 00 157 ffa flash programming frequ ency high byte ffreqh 00 158 ffb flash programming frequency low byte ffreql 00 158 ez8 cpu ffc flags ? xx see foot- note 2. ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page notes: 1. xx = undefined. 2. refer to the ez8 cpu core user manual (um0128) .
ps022827-1212 p r e l i m i n a r y reset, stop mode recovery and low z8 encore! xp ? f082a series product specification 22 reset, stop mode recovery and low voltage detection the reset controller within the z8 encore! xp f082a series controls reset and stop mode recovery operation and provides indication of low su pply voltage conditions. in typical operation, the following events cause a reset: ? power-on reset (por) ? voltage brown-out (vbo) ? watchdog timer time-out (when configured by the wdt_res flash option bit to ini- tiate a reset) ? external reset pin assertion (when the alternate reset function is enabled by the gpio register) ? on-chip debugger initiated re set (ocdctl[0] set to 1) ? when the device is in stop mode, a stop mode reco very is initiated by either of the fol- lowing occurrences: ? watchdog timer time-out ? gpio port input pin transition on an enabled stop mode recovery source ? the low voltage detection circuitry on the device (available on the 8-pin product versions only) performs the fo llowing functions: ? generates the vbo reset when the supply voltage drops below a minimum safe level. ? generates an interrupt when th e supply voltage drops below a user-defined level (8-pin devices only). reset types the z8 encore! xp f082a series provides severa l different types of r eset operation. stop mode recovery is considered as a form of rese t. table 8 lists the types of reset and their operating characteristics. the sy stem reset is longer if the external crystal oscillator is enabled by the flash option bits, allowing additional time for oscillator start-up.
ps022827-1212 p r e l i m i n a r y reset types z8 encore! xp ? f082a series product specification 23 during a system reset or stop mode recovery , the internal precision oscillator requires 4 s to start up. then the z8 encore! xp f082a series device is held in reset for 66 cycles of the internal precision oscillator. if the crystal oscillator is enabled in the flash option bits, this reset period is increased to 5000 ipo cycles. when a reset occurs because of a low voltage condition or power-on reset (por), this delay is measured from the time that the supply voltage first exceeds the po r level. if the external pin reset remains asserted at the end of the reset period, the device remains in reset until the pin is deas- serted. at the beginning of reset, all gpio pins are co nfigured as inputs with pull-up resistor dis- abled, except pd0 (or pa2 on 8-pin devices) wh ich is shared with the reset pin. on reset, the pd0 is configured as a bidirectional open-dr ain reset. the pin is internally driven low during port reset, after which the user code may reconfigure this pin as a general purpose output. during reset, the ez8 cpu and on-chip peripher als are idle; however, the on-chip crystal oscillator and watchdog timer oscillator continue to run. upon reset, control registers w ithin the register file that have a defined reset value are loaded with their reset values. other control registers (including the stack pointer, regis- ter pointer and flags) and general-purpose ram are undefined following reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. prog ram execution begins at the reset vector address. as the control registers are reinitialized by a system reset, th e system clock after reset is always the ipo. the software must reconfigur e the oscillator control block, such that the correct system clock source is enabled and selected. table 8. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as app licable) reset 66 in ternal precision oscillator cycles system reset with crystal oscillator enabled reset (as applicable) res et 5000 internal precision oscillator cycles stop mode recovery un affected, except wdt_ctl and osc_ctl registers reset 66 internal precision oscillator cycles + ipo startup time stop mode recovery with crystal oscillator enabled unaffected, except wdt_ctl and osc_ctl registers reset 5000 internal prec ision oscillator cycles
ps022827-1212 p r e l i m i n a r y reset sources z8 encore! xp ? f082a series product specification 24 reset sources table 9 lists the possible sources of a system reset. power-on reset z8 encore! xp f082a series devices contain an internal power-on reset circuit. the por circuit monitors the supply voltage and holds the device in the reset state until the supply voltage reaches a safe operating level. after the supply voltage exceeds the por voltage threshold (v por ), the device is held in the r eset state until the por counter has timed out. if the crystal oscillator is enable d by the option bits, this time-out is longer. after the z8 encore! xp f082a series device exits the power-on reset state, the ez8 cpu fetches the reset vector. fo llowing power-on reset, the por status bit in the reset status (rststat) register is set to 1. figure 5 displays power-on reset operation. see electrical characteristics on page 221 for the por threshold voltage (v por ). table 9. reset sources and resulting reset type operating mode reset source special conditions normal or halt modes power-on reset/voltage brown- out reset delay begins after supply voltage exceeds por level. watchdog timer time-out ? when configured for reset none. reset pin assertion all reset pulses less than three system clocks in width are ignored. on-chip debugger initiated reset ? (ocdctl[0] set to 1) system reset, except the on-chip debugger is unaffected by the reset. stop mode power-on reset/voltage brown- out reset delay begins after supply voltage exceeds por level. reset pin assertion all reset pulses less than the specified analog delay are ignored. see table 131 on page 229 . dbg pin driven low none.
ps022827-1212 p r e l i m i n a r y reset sources z8 encore! xp ? f082a series product specification 25 voltage brown-out reset the devices in the z8 encore! xp f082a series provide low voltage brown-out (vbo) protection. the vbo circuit senses when the supply voltage drops to an unsafe level (below the vbo threshold voltage) and forces the device into the reset state. while the supply voltage remains below the power-on reset voltage threshold (v por ), the vbo block holds the device in the reset. after the supply voltage again exceeds the power-on reset voltage threshold, the device progresses through a full system reset sequenc e, as described in the power-on reset sec- tion. following power-on rese t, the por status bit in the reset status (rststat) regis- ter is set to 1. figure 6 displays voltage brown-out operation. see the electrical characteristics chapter on page 226 for the vbo and por threshold voltages (v vbo and v por ). the voltage brown-out circuit can be either enabled or disabled during stop mode. operation during stop mode is set by the vbo_ao flash option bit. see the flash option bits chapter on page 159 for information about configuring vbo_ao. figure 5. power-on reset operation v cc = 0.0 v v cc = 3.3v v por v vbo internal precision internal reset signal program execution oscillator start-up por counter delay optional xtal counter delay oscillator crystal oscillator note: not to scale
ps022827-1212 p r e l i m i n a r y reset sources z8 encore! xp ? f082a series product specification 26 the por level is greater than the vbo leve l by the specified hysteresis value. this ensures that the device undergoes a power- on reset after recove ring from a vbo condi- tion. watchdog timer reset if the device is operating in normal or halt mode, the watchdog timer can initiate a system reset at time-out if the wdt_res flash option bit is programmed to 1, i.e., the unprogrammed state of the wdt_res flash option bit. if the bit is programmed to 0, it configures the watchdog timer to cause an interrupt, not a system reset, at time-out. the wdt bit in the reset status (rststat) regi ster is set to signify that the reset was initiated by the watchdog timer. external reset input the reset pin has a schmitt-triggered input and an internal pull-up resistor. once the reset pin is asserted for a minimum of four sy stem clock cycles, th e device progresses through the system reset sequence. because of the possible asynchronicity of the system clock and reset signals, the required reset duration may be as short as three clock periods figure 6. voltage brown-out reset operation vcc = 3.3v v por v vbo internal reset signal program execution program execution voltage brown-out vcc = 3.3 v system clock por counter delay note: not to scale
ps022827-1212 p r e l i m i n a r y stop mode recovery z8 encore! xp ? f082a series product specification 27 and as long as four. a reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. while the reset input pin is asserted low, the z8 encore! xp f082a series devices remain in the reset state. if the reset pin is held low beyond the system reset time- out, the device exits the reset state on th e system clock rising edge following reset pin deassertion. following a system re set initiated by the external reset pin, the ext sta- tus bit in the reset status (rststat) register is set to 1. external reset indicator during system reset or when en abled by the gpio logic (see table 20 on page 46 ), the reset pin functions as an open-dra in (active low) reset mode indicator in addition to the input functionality. this reset output feature allows a z8 encore! xp f082a series device to reset other components to which it is connecte d, even if that reset is caused by internal sources such as por, vbo or wdt events. after an internal reset event occurs, the internal circu itry begins driving the reset pin low. the reset pin is held low by the internal circuitry until the appropriate delay listed in table 8 has elapsed. on-chip debugger initiated reset a power-on reset can be initiated using the on-chip debugger by se tting the rst bit in the ocd control register. the on-chip debugger block is not reset but the rest of the chip goes through a normal system reset. th e rst bit automatically clears during the sys- tem reset. following the system reset the po r bit in the reset status (rststat) register is set. stop mode recovery stop mode is entered by execution of a stop instruction by the ez8 cpu. see the low- power modes chapter on page 32 for detailed stop mode information. during stop mode recovery (smr), the cpu is held in re set for 66 ipo cycles if the crystal oscillator is disabled or 5000 cycles if it is enabled. the smr delay (see table 135 on page 233) t smr , also includes the time requ ired to start up the ipo. stop mode recovery does not affect on-chi p registers other than the watchdog timer control register (wdtctl) and the oscillator control register (oscctl). after any stop mode recovery, the ipo is enabled and selected as the system clock. if another sys- tem clock source is required, the stop mode recovery code must r econfigure the oscillator control block such that the correct system clock source is enabled and selected. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counte r. program execution begins at the reset vec-
ps022827-1212 p r e l i m i n a r y stop mode recovery z8 encore! xp ? f082a series product specification 28 tor address. following stop mode recovery, the stop bit in the reset status (rststat) register is set to 1. table 10 lists the stop mode recovery sources and resulting actions. the text following provides more detailed information about each of the stop mode recovery sources. stop mode recovery using watchdog timer time-out if the watchdog timer times out during stop mode, the device undergoes a stop mode recovery sequence. in the reset status (rststat) register, the wdt and stop bits are set to 1. if the watchdog timer is configured to generate an interrupt upon time-out and the z8 encore! xp f082a series device is c onfigured to respond to interrupts, the ez8 cpu services the watchdog timer interrupt request following the normal stop mode recovery sequence. stop mode recovery using a gpio port pin transition each of the gpio port pins may be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode recove ry source, a change in the input pin value (from high to low or from low to high) initiates stop mode recovery. smr pulses shorter than specified do not trigger a recovery (see table 135 on page 233). in this instance, the stop bit in the reset status (rststat) register is set to 1. in stop mode, the gpio port input data registers (pxin) are disabled. the port input data registers record the port transition only if the signal stays on the port pin through the end of the stop mode recovery delay. as a result, short pulses on the port pin can initiate stop mode recovery without being written to the port input data register or table 10. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watchdog timer time-out when configured for reset stop mode recovery watchdog timer time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery assertion of external reset pin system reset debug pin driven low system reset note: caution:
ps022827-1212 p r e l i m i n a r y low voltage detection z8 encore! xp ? f082a series product specification 29 without initiating an interrupt (if enabled for that pin). stop mode recovery using the external reset pin when the z8 encore! xp f082a series device is in stop mode and the external reset pin is driven low, a system reset occurs. because of a glitch filter operating on the reset pin, the low pulse must be greater than the mi nimum width specified, or it is ignored. see the electrical characteristics chapter on page 226 for details. low voltage detection in addition to the voltage brown-out (vbo) reset described above, it is also possible to generate an interrupt when the supply voltage drops be low a user-selected value. for details about configuring the low voltage dete ction (lvd) and the threshold levels avail- able, see the trim option bits at address 0003h (tlvd) register on page 166. the lvd function is available on the 8-pin product versions only. when the supply voltage drops below the lvd threshold, the lvd bit of the reset status (rststat) register is set to one. this bit remains one until the low-voltage condition goes away. reading or writing this bit does not clear it. the lvd circuit can also generate an interrupt when so enabled, see the gpio mode interrupt controller chapter on page 55. the lvd bit is not latched; therefore, enablin g the interrupt is the only way to guarantee detection of a transient low voltage event. the lvd functionality de pends on circuitry shared with the vbo block; therefore, dis- abling the vbo also disables the lvd. reset register definitions the following sections de fine the reset registers. reset status register the read-only reset status (rststat) register , shown in table 11, indicates the source of the most recent reset event, indicates a stop mode recovery event and indicates a watchdog timer time-out. reading this register resets the upper four bits to 0. this regis- ter shares its address with the write-o nly watchdog timer control register. table 12 lists the bit settings for re set and stop mode recovery events.
ps022827-1212 p r e l i m i n a r y reset register definitions z8 encore! xp ? f082a series product specification 30 table 11. reset status register (rststat) bit 7 6 5 4 3 2 1 0 field por stop wdt ext reserved lvd reset see descriptions below 00000 r/w rrrrrrrr address ff0h bit description [7] ? por power-on reset indicator if this bit is set to 1, a power-on reset event oc curs. this bit is reset to 0 if a wdt time-out or stop mode recovery occurs. this bit is also reset to 0 when the register is read. [6] ? stop stop mode recovery indicator if this bit is set to 1, a stop mode recovery occurs. if the stop and wdt bits are both set to 1, the stop mode recovery occurs because of a wd t time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery was not caused by a wdt time-out. this bit is reset by a power-on reset or a wdt time-out that occurred while not in stop mode. reading this regis- ter also resets this bit. [5] ? wdt watchdog timer time-out indicator if this bit is set to 1, a wdt time-out occurs . a por resets this pin. a stop mode recovery from a change in an input pin also resets this bit. reading this register rese ts this bit. this read must occur before clearing the wdt interrupt. [4] ? ext external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurs. a power-on reset or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. [3:1] reserved these bits are reserved and must be programmed to 000. [0] ? lvd low voltage detection indicator if this bit is set to 1 the current state of the supply voltage is below the low voltage detection threshold. this value is not latched but is a real-time indicator of th e supply voltage level.
ps022827-1212 p r e l i m i n a r y reset register definitions z8 encore! xp ? f082a series product specification 31 table 12. reset and stop mode recovery bit descriptions reset or stop mode recovery event por stop wdt ext power-on reset 1000 reset using reset pin assertion 0001 reset using watchdog timer time-out 0010 reset using the on-chip debugger (octctl[1] set to 1) 1000 reset from stop mode using dbg pin driven low 1000 stop mode recovery using gpio pin transition 0100 stop mode recovery using watchdog timer time-out 0110
ps022827-1212 p r e l i m i n a r y low-power modes z8 encore! xp ? f082a series product specification 32 low-power modes the z8 encore! xp f082a seri es products contain power-saving features. the highest level of power reduction is provided by the stop mode, in which nearly all device func- tions are powered down. the next lower leve l of power reduction is provided by the halt mode, in which the cpu is powered down. further power savings can be implemented by disabling individual peripheral blocks while in active mode (defined as being in neither stop nor halt mode). stop mode executing the ez8 cpu?s stop instruction pl aces the device into stop mode, powering down all peripherals except the voltage brow n-out detector, the low-power operational amplifier and the watchdog timer. these thre e blocks may also be disabled for additional power savings. specifically, the operating characteristics are: ? primary crystal oscillator and internal precision oscillator are stopped; x in and x out (if previously enabled) are disabled and pa0/pa1 revert to the states programmed by the gpio registers ? system clock is stopped ? ez8 cpu is stopped ? program counter (pc) stops incrementing ? watchdog timer?s internal rc oscillator co ntinues to operate if enabled by the oscil- lator control register ? if enabled, the watchdog time r logic continues to operate ? if enabled for operation in stop mode by th e associated flash option bit, the voltage brown-out protection circuit continues to operate ? low-power operational amplifier continues to operate if enabled by the power control register ? all other on-chip peripherals are idle ? to minimize current in stop mode, all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v cc or gnd). additionally, any gpios config- ured as outputs must also be driven to one of the supply rails. the device can be brought out of stop mode using stop mode recove ry. for more information about stop mode recovery, see the reset, stop mode recovery and low voltage detection chapter on page 22.
ps022827-1212 p r e l i m i n a r y halt mode z8 encore! xp ? f082a series product specification 33 halt mode executing the ez8 cpu?s halt instructio n places the device into halt mode, which powers down the cpu but leaves all other peri pherals active. in halt mode, the operat- ing characteristics are: ? primary oscillator is enable d and continues to operate ? system clock is enabled and continues to operate ? ez8 cpu is stopped ? program counter (pc) stops incrementing ? watchdog timer?s internal rc oscillator continues to operate ? if enabled, the watchdog ti mer continues to operate ? all other on-chip peripherals cont inue to operate, if enabled ? the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? watchdog timer time-out (interrupt or reset) ? power-on reset ? voltage brown-out reset ? external reset pin assertion ? to minimize current in halt mode, all gpio pins that are configured as inputs must be driven to one of the supply rails (v cc or gnd). peripheral-level power control in addition to the stop and halt modes, it is possible to disable each peripheral on each of the z8 encore! xp f082a series devices. disabling a given peripheral minimizes its power consumption. power control register definitions the following sections define the power control registers. power control register 0 each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the bl ock. the default state of the low-power
ps022827-1212 p r e l i m i n a r y power control register definitions z8 encore! xp ? f082a series product specification 34 operational amplifier (lpo) is off. to use the lpo, clear the lpo bit, turning it on. clearing this bit might interfere with norm al adc measurements on ana0 (the lpo out- put). this bit enables the amplifier even in st op mode. if the amplifie r is not required in stop mode, disable it. failure to perform this results in stop mode currents greater than specified. this register is only reset during a por sequence. other system reset events do not affect it. table 13. power control register 0 (pwrctl0) bit 7 6 5 4 3 2 1 0 field lpo reserved vbo temp adc comp reserved reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f80h bit description [7] ? lpo low-power operationa l amplifier disable 0 = lpo is enabled (this applies even in stop mode). 1 = lpo is disabled. [6:5] reserved these bits are reserved and must be programmed to 00. [4] ? vbo voltage brown-out detector disable this bit and the vbo_ao flash option bit must bo th enable the vbo for the vbo to be active. 0 = vbo enabled. 1 = vbo disabled. [3] ? temp temperature sensor disable 0 = temperature sensor enabled. 1 = temperature sensor disabled. [2] ? adc analog-to-digital converter disable 0 = analog-to-digital converter enabled. 1 = analog-to-digital converter disabled. [1] ? comp comparator disable 0 = comparator is enabled. 1 = comparator is disabled. [0] reserved this bit is reserved and must be programmed to 0. note:
ps022827-1212 p r e l i m i n a r y power control register definitions z8 encore! xp ? f082a series product specification 35 asserting any power control bit disables the targeted block regardless of any enable bits contained in the target block?s control registers. note:
ps022827-1212 p r e l i m i n a r y general-purpose input/output z8 encore! xp ? f082a series product specification 36 general-purpose input/output the z8 encore! xp f082a series products support a maximum of 25 port pins (ports a? d) for general-purpose input/output (gpio) op erations. each port contains control and data registers. the gpio control registers de termine data direction, open-drain, output drive current, programmable pull-ups, stop mode recovery functiona lity and alternate pin functions. each port pin is individually programmable. in addition, the port c pins are capable of direct led drive at programmable drive strengths. gpio port availability by device table 14 lists the port pins availa ble with each device and package type. table 14. port availability by device and package type devices package adc port a port b port c port d total i/o z8f082asb, z8f082 apb, z8f082aqb z8f042asb, z8f042 apb, z8f042aqb z8f022asb, z8f022 apb, z8f022aqb z8f012asb, z8f012 apb, z8f012aqb 8-pin yes [5:0] no no no 6 z8f081asb, z8f081 apb, z8f081aqb z8f041asb, z8f041 apb, z8f041aqb z8f021asb, z8f021 apb, z8f021aqb z8f011asb, z8f011apb, z8f011aqb 8-pin no [5:0] no no no 6 z8f082aph, z8f082ahh, z8f082ash z8f042aph, z8f042ahh, z8f042ash z8f022aph, z8f022ahh, z8f022ash z8f012aph, z8f012ahh, z8f012ash 20-pin yes [7:0] [3:0] [3:0] [0] 17 z8f081aph, z8f081ahh, z8f081ash z8f041aph, z8f041ahh, z8f041ash z8f021aph, z8f021ahh, z8f021ash z8f011aph, z8f011ahh, z8f011ash 20-pin no [7:0] [3:0] [3:0] [0] 17 z8f082apj, z8f082asj, z8f082ahj z8f042apj, z8f042asj, z8f042ahj z8f022apj, z8f022asj, z8f022ahj z8f012apj, z8f012asj, z8f012ahj 28-pin yes [7:0] [5:0] [7:0] [0] 23 z8f081apj, z8f081asj, z8f081ahj z8f041apj, z8f041asj, z8f041ahj z8f021apj, z8f021asj, z8f021ahj z8f011apj, z8f011asj, z8f011ahj 28-pin no [7:0] [7:0] [7:0] [0] 25
ps022827-1212 p r e l i m i n a r y architecture z8 encore! xp ? f082a series product specification 37 architecture figure 7 displays a simplified block diagram of a gpio port pin. in this figure, the ability to accommodate alternate functions and variab le port current drive strength is not dis- played. gpio alternate functions many of the gpio port pins can be used for general-purpose i/o and access to on-chip peripheral functions such as the timers and serial communication de vices. the port a?d alternate function subregisters configure these pins for either general-purpose i/o or alternate function operation. when a pin is conf igured for alternate fu nction, control of the port pin direction (input/output) is passed from the port a?d data direction registers to the alternate function assigned to this pin. table 15 on page 40 lists th e alternate functions possible with each port pin. for those pins w ith more one alternate function, the alternate function is defined through alternate func tion sets subregisters afs1 and afs2. the crystal oscillator fu nctionality is not controlled by th e gpio block. when the crystal oscillator is enabled in the os cillator control block, the gpio functionality of pa0 and pa1 is overridden. in that case, th ose pins function as input and output for the crystal oscillator. figure 7. gpio port pin block diagram dq dq dq gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt-trigger
ps022827-1212 p r e l i m i n a r y direct led drive z8 encore! xp ? f082a series product specification 38 pa0 and pa6 contain two different timer fu nctions, a timer input and a complementary timer output. both of these fu nctions require the same gpio configuration, the selection between the two is based on the timer mode. see the timers chapter on page 70 for more details. for pins with multiple altern ate functions, zilog recommends writing to the afs1 and afs2 subregisters before enab ling the alternate function via the af subregister. as a re- sult, spurious transitions th rough unwanted alternate func tion modes will be prevented. direct led drive the port c pins provide a current sinked output capable of driving an led without requir- ing an external resistor. the output sinks cu rrent at programmable levels of 3 ma, 7 ma, 13 ma and 20 ma. this mode is enabled through the led control registers. the led drive enable (leden) register turns on th e drivers. the led drive level (ledlvlh and ledlvll) registers select the sink current. for correct function, the led anode must be connected to v dd and the cathode to the gpio pin. using all port c pins in led drive mode with maximum current may result in excessive total current. see the electrical characteristics chapter on page 226 for the max- imum total current for the applicable package. shared reset pin on the 20- and 28-pin devices, the pd0 pin sh ares function with a bidirectional reset pin. unlike all other i/o pins, this pin does not de fault to gpio function on power-up. this pin acts as a bidirectional input/open-drain output reset until the software reconfigures it. the pd0 pin is an output-only open drain when in gpio mode. there are no pull-up, high drive, or stop mode recovery source features associated with the pd0 pin. on the 8-pin product versions, the reset pin is shared with pa2, but the pin is not limited to output-only when in gpio mode. if pa2 on the 8-pin product is reconfigured as an input, ensure that no external stimulus drives the pin low during any reset seque nce. since pa2 returns to its reset alternate function during system resets, driving it low holds the chip in a reset state until the pin is released. caution: caution:
ps022827-1212 p r e l i m i n a r y shared debug pin z8 encore! xp ? f082a series product specification 39 shared debug pin on the 8-pin version of this device only, the debug pin shares function with the pa0 gpio pin. this pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. if the unlock sequence is present, the debug func tion is unlocked and the pin no longer func- tions as a gpio pin. if it is not present, the debug feature is disabled until/unless another reset event occurs. for more details, see the on-chip debugger chapter on page 180 . crystal oscillator override for systems using a crystal oscillator, pa0 and pa1 are used to connect the crystal. when the crystal oscillator is enable d, the gpio settings are overridden and pa0 and pa1 are disabled. see the oscillator control register de finitions section on page 196 for details. 5 v tolerance all six i/o pins on the 8-pin devices are 5 v-tolerant, unless the programmable pull-ups are enabled. if the pull-ups are en abled and inputs higher than v dd are applied to these parts, excessive current flows through thos e pull-up devices and can damage the chip. in the 20- and 28-pin versions of this devi ce, any pin which shares functionality with an adc, crystal or comparator port is not 5 v-tolerant, including pa[1:0], pb[5:0] and pc[2:0]. all other signal pins are 5 v-tolerant and can safely handle inputs higher than v dd except when the programm able pull-ups are enabled. external clock setup for systems using an external ttl drive, pb 3 is the clock source for 20- and 28-pin devices. in this case, configure pb3 for a lternate function clkin. write the oscillator control (oscctl) register such that the ex ternal oscillator is selected as the system clock. see the oscillator control register defi nitions section on page 196 for details. for 8-pin devices, use pa1 instead of pb3. note:
ps022827-1212 p r e l i m i n a r y external clock setup z8 encore! xp ? f082a series product specification 40 table 15. port alternate function mapping (non 8-pin parts) port pin mnemonic alternate function description alternate function set register afs1 port a 1,2 pa0 t0in/t0out timer 0 input/timer 0 output complement n/a reserved pa1 t0out timer 0 output reserved pa2 de0 uart 0 driver enable reserved pa3 cts0 uart 0 clear to send reserved pa4 rxd0/irrx0 uart 0/irda 0 receive data reserved pa5 txd0/irtx0 uart 0/irda 0 transmit data reserved pa6 t1in/t1out timer 1 input/timer 1 output complement reserved pa7 t1out timer 1 output reserved notes: 1. because there is only a single alternate function for each port a pin, the al ternate function set registers are not implemented for port a. enabling alternate function sele ctions automatically enables the associated alternate function. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 2. whether pa0/pa6 takes on the timer input or timer outp ut complement function depends on the timer configura- tion. see the timer pin signal operation section on page 84 for details. 3. because there are at most two choice s of alternate function for any pin of port b, the altern ate function set register afs2 is not used to select the function. al ternate function selection must also be enabled. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 4. v ref is available on pb5 in 28-pin products and on pc2 in 20-pin parts. 5. because there are at most two choice s of alternate function for any pin of port c, the alternate function set register afs2 is not used to select the function. al ternate function selection must also be enabled. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 6. because there is only a single alternate function for t he port pd0 pin, the alternate function set registers are not implemented for port d. enabling alternate function selections automatically enables the associated alter- nate function. see the port a?d alternate func tion subregisters (pxaf) section on page 47 for details.
ps022827-1212 p r e l i m i n a r y external clock setup z8 encore! xp ? f082a series product specification 41 port b 3 pb0 reserved af s1[0]: 0 ana0/ampout adc analog i nput/lpo output afs1[0]: 1 pb1 reserved af s1[1]: 0 ana1/ampinn adc analog inpu t/lpo input (n) afs1[1]: 1 pb2 reserved af s1[2]: 0 ana2/ampinp adc analog inpu t/lpo input (p) afs1[2]: 1 pb3 clkin external clock input afs1[3]: 0 ana3 adc analog input afs1[3]: 1 pb4 reserved af s1[4]: 0 ana7 adc analog input afs1[4]: 1 pb5 reserved af s1[5]: 0 v ref 4 adc voltage reference afs1[5]: 1 pb6 reserved af s1[6]: 0 reserved afs1[6]: 1 pb7 reserved af s1[7]: 0 reserved afs1[7]: 1 table 15. port alternate function mapping (non 8-pin parts) (continued) port pin mnemonic alternate function description alternate function set register afs1 notes: 1. because there is only a single alternate function for each port a pin, the al ternate function set registers are not implemented for port a. enabling alternate function sele ctions automatically enables the associated alternate function. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 2. whether pa0/pa6 takes on the timer input or timer outp ut complement function depends on the timer configura- tion. see the timer pin signal operation section on page 84 for details. 3. because there are at most two choice s of alternate function for any pin of port b, the altern ate function set register afs2 is not used to select the function. al ternate function selection must also be enabled. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 4. v ref is available on pb5 in 28-pin products and on pc2 in 20-pin parts. 5. because there are at most two choice s of alternate function for any pin of port c, the alternate function set register afs2 is not used to select the function. al ternate function selection must also be enabled. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 6. because there is only a single alternate function for t he port pd0 pin, the alternate function set registers are not implemented for port d. enabling alternate function selections automatically enables the associated alter- nate function. see the port a?d alternate func tion subregisters (pxaf) section on page 47 for details.
ps022827-1212 p r e l i m i n a r y external clock setup z8 encore! xp ? f082a series product specification 42 port c 5 pc0 reserved afs1[0]: 0 ana4/cinp adc or comparator input afs1[0]: 1 pc1 reserved afs1[1]: 0 ana5/cinn adc or comparator input afs1[1]: 1 pc2 reserved afs1[2]: 0 ana6/v ref 4 adc analog input or adc voltage refer- ence afs1[2]: 1 pc3 cout comparator output afs1[3]: 0 reserved afs1[3]: 1 pc4 reserved afs1[4]: 0 afs1[4]: 1 pc5 reserved afs1[5]: 0 afs1[5]: 1 pc6 reserved afs1[6]: 0 afs1[6]: 1 pc7 reserved afs1[7]: 0 afs1[7]: 1 port d 6 pd0 reset external reset n/a table 15. port alternate function mapping (non 8-pin parts) (continued) port pin mnemonic alternate function description alternate function set register afs1 notes: 1. because there is only a single alternate function for each port a pin, the al ternate function set registers are not implemented for port a. enabling alternate function sele ctions automatically enables the associated alternate function. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 2. whether pa0/pa6 takes on the timer input or timer outp ut complement function depends on the timer configura- tion. see the timer pin signal operation section on page 84 for details. 3. because there are at most two choice s of alternate function for any pin of port b, the altern ate function set register afs2 is not used to select the function. al ternate function selection must also be enabled. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 4. v ref is available on pb5 in 28-pin products and on pc2 in 20-pin parts. 5. because there are at most two choice s of alternate function for any pin of port c, the alternate function set register afs2 is not used to select the function. al ternate function selection must also be enabled. see the port a?d alternate function subregisters (pxaf) section on page 47 for details. 6. because there is only a single alternate function for t he port pd0 pin, the alternate function set registers are not implemented for port d. enabling alternate function selections automatically enables the associated alter- nate function. see the port a?d alternate func tion subregisters (pxaf) section on page 47 for details.
ps022827-1212 p r e l i m i n a r y external clock setup z8 encore! xp ? f082a series product specification 43 table 16. port alternate function mapping (8-pin parts) port pin mnemonic alternate function description alternate function select register afs1 alternate function select register afs2 port a pa0 t0in timer 0 input afs1[0]: 0 afs2[0]: 0 reserved afs1[0]: 0 afs2[0]: 1 reserved afs1[0]: 1 afs2[0]: 0 t0out timer 0 output complement afs1[0]: 1 afs2[0]: 1 pa1 t0out timer 0 output afs1[1]: 0 afs2[1]: 0 reserved afs1[1]: 0 afs2[1]: 1 clkin external clock input afs1[1]: 1 afs2[1]: 0 analog functions 1 adc analog input/v ref afs1[1]: 1 afs2[1]: 1 pa2 de0 uart 0 driver enable afs1[2]: 0 afs2[2]: 0 reset external reset a fs1[2]: 0 afs2[2]: 1 t1out timer 1 output afs1[2]: 1 afs2[2]: 0 reserved afs1[2]: 1 afs2[2]: 1 pa3 cts0 uart 0 clear to send afs1[3]: 0 afs2[3]: 0 cout comparator output afs1[3]: 0 afs2[3]: 1 t1in timer 1 input afs1[3]: 1 afs2[3]: 0 analog functions 2 adc analog input/lpo input (p) afs1[3]: 1 afs2[3]: 1 pa4 rxd0 uart 0 receive data afs1[4]: 0 afs2[4]: 0 reserved afs1[4]: 0 afs2[4]: 1 reserved afs1[4]: 1 afs2[4]: 0 analog functions 2 adc/comparator input (n)/lpo input (n) afs1[4]: 1 afs2[4]: 1 pa5 txd0 uart 0 transmit da ta afs1[5]: 0 afs2[5]: 0 t1out timer 1 output complement afs1[5]: 0 afs2[5]: 1 reserved afs1[5]: 1 afs2[5]: 0 analog functions 2 adc/comparator input (p) lpo output afs1[5]: 1 afs2[5]: 1 notes: 1. analog functions include adc inputs, adc reference, comparator inputs and lpo ports. 2. the alternate function selection must be enabled; see the port a?d alternate function subregisters (pxaf) sec- tion on page 47 for details.
ps022827-1212 p r e l i m i n a r y gpio interrupts z8 encore! xp ? f082a series product specification 44 gpio interrupts many of the gpio port pins can be used as interrupt sources. some port pins can be con- figured to generate an interrupt request on eith er the rising edge or falling edge of the pin input signal. other port pin interrupt sources generate an interrupt when any edge occurs (both rising and falling). see the gpio mode interrupt controller chapter on page 55 for more information about inte rrupts using the gpio pins. gpio control register definitions four registers for each port provide access to gpio control, input data and output data. table 17 lists these port registers. use the port a?d address and control registers together to provide access to subregiste rs for port configuration and control. table 17. gpio port registers and subregisters port register mnemonic port register name p x addr port a?d address regist er; selects subregisters. p x ctl port a?d control register; prov ides access to subregisters. p x in port a?d input data register. p x out port a?d output data register. port subregister mnemonic port register name p x dd data direction. p x af alternate function. p x oc output control (open-drain). p x hde high drive enable. p x smre stop mode recovery source enable. p x pue pull-up enable. pxafs1 alternate function set 1. pxafs2 alternate function set 2.
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 45 port a?d address registers the port a?d address registers select the gp io port functionality accessible through the port a?d control registers. the port a?d address and control registers combine to pro- vide access to all gpio port controls; see tables 18 and 19. table 18. port a?d gpio address registers (p x addr) bit 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd0h, fd4h, fd8h, fdch bit description [7:0] ? paddrx port address the port address selects one of the subregisters accessible through the port control register. note: x indicates the specific gpio port pin number (7?0). table 19. port a?d gpio address registers by bit description paddr[7:0] port control subregister accessible using the port a?d control registers 00h no function. provides some protection against accidental port reconfiguration. 01h data direction. 02h alternate function. 03h output control (open-drain). 04h high drive enable. 05h stop mode recove ry source enable. 06h pull-up enable. 07h alternate function set 1. 08h alternate function set 2. 09h?ffh no function.
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 46 port a?d control registers the port a?d control registers set the gpio port operation. the value in the correspond- ing port a?d address register determines whic h subregister is read from or written to by a port a?d control register transaction; see table 20. port a?d data dire ction subregisters the port a?d data direction subregister is accessed through the port a?d control regis- ter by writing 01h to the port a?d address register; see table 21. table 20. port a?d control registers (pxctl) bit 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd1h, fd5h, fd9h, fddh bit description [7:0] ? pctlx port control the port control register provides access to all subregisters that configure the gpio port operation. note: x indicates the specific gpio port pin number (7?0). table 21. port a?d data di rection subregisters (pxdd) bit 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 01h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? ddx data direction these bits control the direction of the associated port pin. port alternate function operation overrides the data direction register setting. 0 = output. data in the port a?d output data register is driven onto the port pin. 1 = input. the port pin is sampled and the value written into the port a?d input data register. the output driver is tristated. note: x indicates the specific gpio port pin number (7?0).
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 47 port a?d alternate fu nction subregisters the port a?d alternate functio n subregister, shown in tabl e 22, is accessed through the port a?d control register by writing 02h to the port a?d address register. the port a? d alternate function subregisters enable the alternate function selection on pins. if dis- abled, pins functions as gpio. if enabled, se lect one of four alternate functions using alternate function set subregiste rs 1 and 2 as described in the the port a?d alternate function set 1 subregisters section on page 50 , the gpio alternate functions section on page 37 and the port a?d alternate function set 2 subregisters section on page 51. see the gpio alternate functions section on page 37 to determine the alternate function asso- ciated with each port pin. do not enable alternate functions for gpio po rt pins for which there is no associated al- ternate function. failure to follow this gu ideline can result in unpredictable operation. port a?d output c ontrol subregisters the port a?d output control subregister, show n in table 23, is accessed through the port a?d control register by writing 03h to the port a?d address register. setting the bits in the port a?d output control subr egisters to 1 configures the specified port pins for open- drain operation. these subregisters affect the pi ns directly and, as a result, alternate func- tions are also affected. table 22. port a?d alternate function subregisters (pxaf) bit 7 6 5 4 3 2 1 0 field af7 af6 af5 af4 af3 af2 af1 af0 reset 00h (ports a?c); 01h (port d); 04h (port a of 8-pin device) r/w r/w address if 02h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? afx port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a?d data direction subregister determines the direction of the pin. 1 = the alternate function selected through alte rnate function set subregisters is enabled. port pin operation is controlled by the alternate function. note: x indicates the specific gpio port pin number (7?0). caution:
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 48 port a?d high drive enable subregisters the port a?d high drive enable subregister, shown in table 24, is accessed through the port a?d control register by writing 04h to the port a?d address register. setting the bits in the port a?d high driv e enable subregisters to 1 conf igures the specified port pins for high current output drive operation. th e port a?d high drive enable subregister affects the pins directly and, as a resu lt, alternate functions are also affected. table 23. port a?d output control subregisters (pxoc) bit 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00h (ports a-c); 01h (port d) r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 03h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? pocx port output control these bits function independently of the altern ate function bit and always disable the drains if set to 1. 0 = the source current is enabled for any output mode unless overridden by the alternate func- tion (push-pull output). 1 = the source current for the associated pin is disabled (open-drain mode). note: x indicates the specific gpio port pin number (7?0). table 24. port a?d high drive enable subregisters (pxhde) bit 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 04h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? phdex port high drive enabled 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. note: x indicates the specific gpio port pin number (7?0).
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 49 port a?d stop mode recovery source enable subregisters the port a?d stop mode recovery source enable subregister, shown in table 25, is accessed through the port a?d control register by writing 05h to the port a?d address register. setting the bits in the port a?d stop mode recovery source enable subregisters to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enable d as a stop mode recovery source initiates stop mode recovery. table 25. port a?d stop mode recovery source enable subregisters (pxsmre) bit 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 05h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? psmrex port stop mode recovery source enabled 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin dur- ing stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mode recovery source. any logic transition on this pin during stop mode initiates stop mode recovery. note: x indicates the specific gpio port pin number (7?0).
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 50 port a?d pull-up enable subregisters the port a?d pull-up enable su bregister, shown in table 26, is accessed through the port a?d control register by writing 06h to the port a?d address register. setting the bits in the port a?d pull-up enable subregisters enab les a weak internal resistive pull-up on the specified port pins. port a?d alternate func tion set 1 subregisters the port a?d alternate function set1 subr egister, shown in table 27, is accessed through the port a?d cont rol register by writing 07h to the port a?d address register. the alternate function set 1 subr egisters selects the alternate function available at a port pin. alternate functions selected by setting or cl earing bits of this register are defined in the gpio alternate functions section on page 37. alternate function selection on port pins must also be enabled as described in the port a? d alternate function subregisters section on page 47. table 26. port a?d pull-up enable subregisters (pxpue) bit 7 6 5 4 3 2 1 0 field ppue7 ppue6 ppue5 ppue4 ppue3 ppue2 ppue1 ppue0 reset 00h (ports a-c); 01h (port d); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 06h in port a ? d address register, accessible through the port a ? d control register bit description [7:0] ? ppuex port pull-up enabled 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. note: x indicates the specific gpio port pin number (7?0). note:
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 51 port a?d alternate func tion set 2 subregisters the port a?d alternate function set 2 subr egister, shown in table 28, is accessed through the port a?d cont rol register by writing 08h to the port a?d address register. the alternate function set 2 subr egisters selects the alternate function available at a port pin. alternate functions selected by setting or cl earing bits of this re gister is defined in table 16 on page 43. alternate function selection on the port pins must also be enabled. see the port a?d alter- nate function subregisters section on page 47 for details. table 27. port a?d alternate function set 1 subregisters (pxafs1) bit 7 6 5 4 3 2 1 0 field pafs17 pafs16 pafs15 pafs14 pafs13 pafs12 pafs11 pafs10 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 07h in port a?d address register, access ible through the port a?d control register bit description [7:0] ? pafsx port alternate function set 1 0 = port alternate function selected, as defined in tables 15 and 16 on page 43. 1 = port alternate function selected, as defined in tables 15 and 16 on page 43. note: x indicates the specific gpio port pin number (7?0). table 28. port a?d alternate function set 2 subregisters (pxafs2) bit 7 6 5 4 3 2 1 0 field pafs27 pafs26 pafs25 pafs24 pafs23 pafs22 pafs21 pafs20 reset 00h (all ports of 20/28 pin devices); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w address if 08h in port a?d address register, access ible through the port a?d control register bit description [7] ? pafs2x port alternate function set 2 0 = port alternate function selected, as defined in table 16. 1 = port alternate function selected, as defined in table 16. note: x indicates the specific gpio port pin number (7?0). note:
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 52 port a?c input data registers reading from the port a?c input data registers, shown in table 29, return the sampled values from the corresponding po rt pins. the port a?c input data registers are read-only. the value returned for any unused ports is 0. unused ports include those missing on the 8- and 28-pin packages, as well as those missi ng on the adc-enabled 28-pin packages. port a?d output data register the port a?d output data register, shown in ta ble 30, controls the output data to the pins. table 29. port a?c input data registers (pxin) bit 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr address fd2h, fd6h, fdah x = undefined. bit description [7:0] ? pxin port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). note: x indicates the specific gpio port pin number (7?0). table 30. port a?d output data register (p x out) bit 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fd3h, fd7h, fdbh, fdfh bit description [7:0] ? pxout port output data these bits contain the data to be driven to the port pins. the values are only driven if the corre- sponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1 = drive a logical 1 (high). high value is not driven if the drain has been disabled by setting the corresponding port output control register bit to 1. note: x indicates the specific gpio port pin number (7?0).
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 53 led drive enable register the led drive enable register, shown in tabl e 31, activates the controlled current drive. the alternate function register has no control over the led function; therefore, setting the alternate function register to select th e led function is not required. leden bits [7:0] correspond to port c bits [7:0], respectively. led drive level high register the led drive level registers contain two contro l bits for each port c pin, as shown in table 32. these two bits select between four programmable drive leve ls. each pin is indi- vidually programmable. table 31. led drive enable (leden) bit 7 6 5 4 3 2 1 0 field leden[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f82h bit description [7:0] ? ledenx led drive enable these bits determine which port c pins are connected to an internal current sink. 0 = tristate the port c pin. 1 = enable controlled current sink on the port c pin. note: x indicates the specific gpio port pin number (7?0). table 32. led drive level high register (ledlvlh) bit 7 6 5 4 3 2 1 0 field ledlvlh[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f83h bit description [7:0] ? ledlvlhx led level high bit {ledlvlh, ledlvll} select one of four progra mmable current drive levels for each port c pin. 00 = 3 ma 01 = 7 ma 10 = 13 ma 11 = 20 ma note: x indicates the specific gpio port pin number (7?0).
ps022827-1212 p r e l i m i n a r y gpio control register definitions z8 encore! xp ? f082a series product specification 54 led drive level low register the led drive level registers contain two cont rol bits for each port c pin (table 33). these two bits select between four programmab le drive levels. each pin is individually programmable. table 33. led drive level low register (ledlvll) bit 7 6 5 4 3 2 1 0 field ledlvll[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f84h bit description [7:0] ? ledlvllx led level low bit {ledlvlh, ledlvll} select one of four program mable current drive levels for each port c pin. 00 = 3 ma 01 = 7 ma 10 = 13 ma 11 = 20 ma note: x indicates the specific gpio port pin number (7?0).
ps022827-1212 p r e l i m i n a r y gpio mode interrupt controller z8 encore! xp ? f082a series product specification 55 gpio mode interrupt controller the interrupt controller on the z8 encore! xp f082a series products prioritizes the inter- rupt requests from the on-chip peripherals and the gpio port pins. the features of inter- rupt controller include: ? 20 possible interrupt sources with 18 unique interrupt vectors: ? twelve gpio port pin interrupt sourc es (two interrupt vectors are shared) ? eight on-chip peripheral interrupt sources (two interrupt vectors are shared) ? ? flexible gpio interrupts: ? eight selectable rising and falling edge gpio interrupts ? four dual-edge interrupts ? ? three levels of individually programmable interrupt priority ? watchdog timer and lvd can be configured to generate an interrupt ? supports vectored and polled interrupts ? interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the cpu and the interrupting pe ripheral. when the service routine is com- pleted, the cpu returns to the operation from wh ich it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt controller has no effect on ope ration. for more inform ation about interrupt servicing by the ez8 cpu, refer to the ez8 cpu core user manual (um0128) , which is available for download on www.zilog.com . interrupt vector listing table 34 lists all of the interrupts available in order of priority. the interrupt vector is stored with the most-significant byte (msb) at the even program memory address and the least-significant byte (lsb) at the following odd program memory address. some port interrupts are not av ailable on the 8- and 20-pin packages. the adc interrupt is unavailable on devices not containing an adc. note:
ps022827-1212 p r e l i m i n a r y interrupt vector listing z8 encore! xp ? f082a series product specification 56 table 34. trap and interrupt vectors in order of priority priority program memory ? vector address interrupt or trap source highest 0002h reset (not an interrupt) 0004h watchdog timer (see watchdog timer) 003ah primary oscillator fail trap (not an interrupt) 003ch watchdog oscillator fail trap (not an interrupt) 0006h illegal instruction trap (not an interrupt) 0008h reserved 000ah timer 1 000ch timer 0 000eh uart 0 receiver 0010h uart 0 transmitter 0012h reserved 0014h reserved 0016h adc 0018h port a pin 7, selectable rising or falling input edge or lvd (see reset, stop mode recovery and low voltage detection) 001ah port a pin 6, selectable rising or falling input edge or comparator output 001ch port a pin 5, selectable rising or falling input edge 001eh port a pin 4, selectable rising or falling input edge 0020h port a pin 3, selectable rising or falling input edge 0022h port a pin 2, selectable rising or falling input edge 0024h port a pin 1, selectable rising or falling input edge 0026h port a pin 0, selectable rising or falling input edge 0028h reserved 002ah reserved 002ch reserved 002eh reserved 0030h port c pin 3, both input edges 0032h port c pin 2, both input edges 0034h port c pin 1, both input edges lowest 0036h port c pin 0, both input edges 0038h reserved
ps022827-1212 p r e l i m i n a r y architecture z8 encore! xp ? f082a series product specification 57 architecture figure 8 displays the interrupt controller block diagram. operation this section describes th e operational aspects of the following functions. master interrupt enable : see page 57 interrupt vectors and priority : see page 58 interrupt assertion : see page 58 software interrupt assertion : see page 59 watchdog timer interrupt assertion : see page 59 master interrupt enable the master interrupt enable bit ( irqe ) in the interrupt control register globally enables and disables interrupts. interrupts are globally enabled by any of the following actions: ? execution of an ei (enable interrupt) instruction ? execution of an iret (retur n from interrupt) instruction figure 8. interrupt controller block diagram vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 58 ? writing a 1 to the irqe bit in the interrupt control register ? interrupts are globally disabled by any of the following actions: ? execution of a disable interrupt (di) instruction ? ez8 cpu acknowledgement of an interrupt service request from the interrupt controller ? writing a 0 to the irqe bit in the interrupt control register ? reset ? execution of a trap instruction ? illegal instruction trap ? primary oscillator fail trap ? watchdog oscillator fail trap interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest priority and level 1 is the lowest priority. if all of the interrupts are enable d with identical interrupt prior ity (all as level 2 interrupts, for example), the interrupt priori ty is assigned from highest to lowest as specified in table 34 on page 56 . level 3 interrupts are always assigned higher priority than level 2 interrupts which, in turn, always are assigned higher pr iority than level 1 interrupts. within each interrupt priority level (level 1, level 2, or level 3), priority is ass igned as specified in table 34, above. reset, watchdog timer inte rrupt (if enabled), primary oscillator fail trap, watchdog oscillator fail trap and illegal instruction trap always have highest (level 3) priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (sin- gle pulse). when the interrupt request is ac knowledged by the ez8 cpu, the correspond- ing bit in the interrupt reques t register is cleared until the next interrupt occurs. writing a 0 to the corresponding bit in the interrupt requ est register likewise clears the interrupt request. zilog recommends not using a coding style that clears bits in the interrupt request reg- isters. all incoming interrupts recei ved between execution of the first ldx command and the final ldx command are lost. see example 1, which follows. caution:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 59 example 1. a poor coding style that can re sult in lost interrupt requests: ldx r0, irq0 ? and r0, mask ? ldx irq0, r0 ? to avoid missing interrupts, use the coding styl e in example 2 to clear bits in the interrupt request 0 register: example 2. a good coding style that av oids lost interrupt requests: andx irq0, mask software interrupt assertion program code can generate interrupts directly. writing a 1 to the correct bit in the interrupt request register triggers an interrupt (assuming that interrupt is enabled). when the inter- rupt request is acknowledged by the ez8 cpu, the bit in the interrupt request register is automatically cleared to 0. zilog recommends not using a coding style to generate software interrupts by setting bits in the interrupt request registers. all inco ming interrupts received between execution of the first ldx command and the final ldx co mmand are lost. see example 3, which fol- lows. example 3. a poor coding style that can re sult in lost interrupt requests: ldx r0, irq0 ? or r0, mask ? ldx irq0, r0 to avoid missing interrupts, use the coding styl e in example 4 to set bits in the interrupt request registers: example 4. a good coding style that av oids lost interrupt requests: orx irq0, mask watchdog timer interrupt assertion the watchdog timer interrupt behavior is different from interrupts generated by other sources. the watchdog timer co ntinues to assert an interrupt as long as the time-out con- dition continues. as it operates on a different (and usually slower) clock domain than the rest of the device, the watchdog timer contin ues to assert this interrupt for many system clocks until the counter rolls over. caution:
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 60 to avoid retriggerings of the watchdog time r interrupt after exiting the associated inter- rupt service routine, zilog r ecommends that the service ro utine continues to read from the rststat register until the wdt bit is cl eared as shown in the following example. clearwdt: ? ldx r0, rststat ; read reset status register to clear wdt bit ? btjnz 5, r0, clearwdt ; loop until bit is cleared interrupt control register definitions for all interrupts other than the watchdog timer interrupt, the primary oscillator fail trap and the watchdog oscillato r fail trap, the interrupt cont rol registers enable individ- ual interrupts, set interrupt prior ities and indicate interrupt requests. interrupt requ est 0 register the interrupt request 0 (irq0) register, shown in table 35, stores th e interrupt requests for both vectored and polled interrupts. when a request is presented to the interrupt con- troller, the corresponding bit in the irq0 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt cont roller passes an interrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), the ez8 cpu can read the interrupt request 0 register to determine if any interrupt requests are pending. table 35. interrupt request 0 register (irq0) bit 7 6 5 4 3 2 1 0 field reserved t1i t0i u0rxi u0t xi reserved reserved adci reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc0h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? t1i timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. [5] ? t0i timer 0 interrupt request 0 = no interrupt request is pending for timer 0. ? 1 = an interrupt request from timer 0 is awaiting service. caution:
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 61 interrupt requ est 1 register the interrupt request 1 (irq1) register, shown in table 36, stores interrupt requests for both vectored and polled interrupts. when a requ est is presented to th e interrupt controller, the corresponding bit in the irq1 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller pa sses an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending. [4] ? u0rxi uart 0 receiver interrupt request 0 = no interrupt request is pending for the uart 0 receiver. ? 1 = an interrupt request from the ua rt 0 receiver is awaiting service. [3] ? u0txi uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. ? 1 = an interrupt request from the uart 0 transmitter is awaiting service. [2:1] reserved these bits are reserved and must be programmed to 00. [0] ? adci adc interrupt request 0 = no interrupt request is pending for the analog-to-digital converter. ? 1 = an interrupt request from the analog-to-digital converter is awaiting service. table 36. interrupt request 1 register (irq1) bit 7 6 5 4 3 2 1 0 field pa7vi pa6ci pa5i pa4i pa3i pa2i pa1i pa0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc3h bit description [7] ? pa7vi port a pin 7 or lvd interrupt request 0 = no interrupt request is pending for gpio port a or lvd. ? 1 = an interrupt request from gpio port a or lvd. [6] ? pa6ci port a pin 6 or compar ator interrupt request 0 = no interrupt request is pending for gpio port a or comparator. ? 1 = an interrupt request from gpio port a or comparator. [5:0] ? pa5i port a pin x interrupt request 0 = no interrupt request is pending for gpio port a pin x. ? 1 = an interrupt request from gpio port a pin x is awaiting service. note: x indicates the specific gpio port pin number (0?5). bit description (continued)
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 62 interrupt requ est 2 register the interrupt request 2 (irq2) register, shown in table 37, stores interrupt requests for both vectored and polled interrupts. when a requ est is presented to th e interrupt controller, the corresponding bit in the irq2 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller pa sses an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 2 register to determine if any interrupt requests are pending. irq0 enable high and low bit registers table 38 describes the priority control for irq0. the irq0 enable high and low bit reg- isters, shown in tables 39 and 40, form a pr iority-encoded enabling for interrupts in the interrupt request 0 register. table 37. interrupt request 2 register (irq2) bit 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc6h bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3:0] ? pcxi port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . ? 1 = an interrupt request from gpio port c pin x is awaiting service. note: x indicates the specific gpio port c pin number (0?3). table 38. irq0 enable and priority encoding irq0enh[ x ]irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 1 1 level 3 high note: x indicates register bits 0?7.
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 63 table 39. irq0 enable hi gh bit register (irq0enh) bit 7 6 5 4 3 2 1 0 field reserved t1enh t0enh u0renh u0 tenh reserved reserved adcenh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc1h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? t1enh timer 1 interrupt reque st enable high bit [5] ? t0enh timer 0 interrupt reque st enable high bit [4] ? u0renh uart 0 receive interrupt request enable high bit [3] ? u0tenh uart 0 transmit interrupt request enable high bit [2:1] reserved these bits are reserved and must be programmed to 00. [0] ? adcenh adc interrupt request enable high bit table 40. irq0 enable low bit register (irq0enl) bit 7 6 5 4 3 2 1 0 field reserved t1enl t0enl u0renl u0 tenl reserved reserved adcenl reset 00000000 r/w r r/w r/w r/w r/w r r r/w address fc2h bit description [7] reserved this bit is reserved and must be programmed to 0. [6] ? t1enl timer 1 interrupt request enable low bit [5] ? t0enl timer 0 interrupt request enable low bit
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 64 irq1 enable high and low bit registers table 41 describes the priority control for irq1. the irq1 enable high and low bit reg- isters, shown in tables 41 and 42, form a pr iority-encoded enabling for interrupts in the interrupt request 1 register. [4] ? u0renl uart 0 receive interrupt request enable low bit [3] ? u0tenl uart 0 transmit interrupt request enable low bit [2:1] reserved these bits are reserved and must be programmed to 00. [0] ? adcenl adc interrupt request enable low bit table 41. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 1 1 level 3 high note: x indicates register bits 0?7. bit description (continued)
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 65 see the shared interrupt select register (irqss) register on page 68 for selection of either the lvd or the comparator as the interrupt source. irq2 enable high and low bit registers table 44 describes the priority control for irq2. the irq2 enable high and low bit reg- isters, shown in tables 44 and 45, form a pr iority-encoded enabling for interrupts in the interrupt request 2 register. table 42. irq1 enable hi gh bit register (irq1enh) bit 7 6 5 4 3 2 1 0 field pa7venh pa6cenh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc4h bit description [7] ? pa7venh port a bit[7] or lvd interrupt request enable high bit [6] ? pa6cenh port a bit[7] or comparator interrupt request enable high bit [5:0] ? paxenh port a bit[ x ] interrupt request enable high bit table 43. irq1 enable low bit register (irq1enl) bit 7 6 5 4 3 2 1 0 field pa7venl pa6cenl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc5h bit description [7] ? pa7venl port a bit[7] or lvd interr upt request enable low bit [6] ? pa6cenl port a bit[6] or comparator interrupt request enable low bit [5:0] ? paxenl port a bit[ x ] interrupt request enable low bit
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 66 table 44. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 1 1 level 3 high note: x indicates register bits 0?7. table 45. irq2 enable hi gh bit register (irq2enh) bit 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc7h bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3] ? c3enh port c3 interrupt requ est enable high bit [2] ? c2enh port c2 interrupt requ est enable high bit [1] ? c1enh port c1 interrupt requ est enable high bit [0] ? c0enh port c0 interrupt requ est enable high bit
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 67 interrupt edge select register the interrupt edge select (ir qes) register, shown in table 47, determines whether an interrupt is generated for the rising edge or falling edge on the selected gpio port a input pin. table 46. irq2 enable low bit register (irq2enl) bit 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fc8h bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3] ? c3enl port c3 interrupt request enable low bit [2] ? c2enl port c2 interrupt request enable low bit [1] ? c1enl port c1 interrupt request enable low bit [0] ? c0enl port c0 interrupt request enable low bit table 47. interrupt edge select register (irqes) bit 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fcdh bit description [7:0] iesx interrupt edge select x 0 = an interrupt request is generated on the falling edge of the pa x input. ? 1 = an interrupt request is generated on the rising edge of the pa x input. note: x indicates the specific gpio port pin number (0?7).
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 68 shared interrupt select register the shared interrupt select (irqss) register , shown in table 48, determines the source of the padxs interrupts. the sh ared interrupt select register selects between port a and alternate sources for the individual interrupts. because these shared interrupts are edge-trigger ed, it is possible to generate an interrupt just by switching from one shared source to another. for this reason, an interrupt must be disabled before switching between sources. table 48. shared interrupt select register (irqss) bit 7 6 5 4 3 2 1 0 field pa7vs pa6cs reserved reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address fceh bit description [7] ? pa7vs pa 7 /lvd selection 0 = pa 7 is used for the interrupt for pa7vs interrupt request. ? 1 = the lvd is used for the interrupt for pa7vs interrupt request. [6] ? pa6cs pa6/comparator selection 0 = pa6 is used for the interrupt for pa6cs interrupt request. ? 1 = the comparator is used for the interrupt for pa6cs interrupt request. [5:0] reserved these bits are reserved and must be programmed to 000000.
ps022827-1212 p r e l i m i n a r y interrupt control register definitions z8 encore! xp ? f082a series product specification 69 interrupt control register the interrupt control (irqctl) register, shown in table 49, contains the master enable bit for all interrupts. table 49. interrupt control register (irqctl) bit 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr address fcfh bit description [7] ? irqe interrupt request enable this bit is set to 1 by executing an ei (enable in terrupts) or iret (interrupt return) instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an interrupt request, reset or by a direct register write of a 0 to this bit.? 0 = interrupts are disabled. ? 1 = interrupts are enabled. [6:0] reserved these bits are reserved and must be programmed to 0000000.
ps022827-1212 p r e l i m i n a r y timers z8 encore! xp ? f082a series product specification 70 timers these z8 encore! xp f082a seri es products contain two 16-bit reloadable timers that can be used for timing, event counting, or ge neration of pulse-width modulated (pwm) sig- nals. the timers? feature include: ? 16-bit reload counter ? programmable prescaler with prescale values from 1 to 128 ? pwm output generation ? capture and compare capability ? external input pin for timer input, clock ga ting, or capture signal. external input pin signal frequency is limited to a maximum of one-fourth the system clock frequency ? timer output pin ? timer interrupt ? in addition to the timers described in this ch apter, the baud rate generator of the uart (if unused) may also provide basic timing fu nctionality. for information about using the baud rate generator as an additional timer, see the universal asynchronous receiver/ transmitter chapter on page 99. architecture figure 9 displays the architecture of the timers.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 71 operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer rolls over to 0000h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer co unts up to the 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system cl ock. upon reaching the reload value, the timer ge nerates an interrupt and the co unt value in the timer high and low byte registers is reset to 0001h . the timer is automatica lly disabled and stops counting. also, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high or from high to low) upon timer reload. if figure 9. timer block diagram 16-bit pwm/compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer block system timer data block output control bus clock input gate input capture input timer interrupt timer output complement
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 72 it is appropriate to have the timer output ma ke a state change at a one-shot time-out (rather than a single cycle pulse), first set th e tpol bit in the timer control register to the start value before enabling one-shot mode. after starting the timer, set tpol to the opposite bit value. observe the following steps for configuring a timer for one-shot mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode. ? set the prescale value. ? set the initial output level (high or low) if using the timer ou tput alternate func- tion. 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in one-shot mode, the system clock always pr ovides the timer inpu t. the timer period is computed via th e following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the reload value, th e timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate func tion is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps for configuring a timer for continuous mode and initiat- ing the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for continuous mode one-shot mode time-out period s ?? reload value s tart value ? prescale ? system clock frequency hz ?? ----------------------------------------------------------------------------------------------------------------- - =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 73 ? set the prescale value ? if using the timer output alternate function, set the initial output level (high or low) ? 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this action only affects the first pass in continuous mode. after the first timer reload in continuous mode, c ounting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt (if appropriate) an d set the timer interrupt priority by writ- ing to the relevant interrupt registers. 5. configure the associated gpio port pin (i f using the timer output function) for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. ? in continuous mode, the system clock alwa ys provides the timer input. the timer period is computed via the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equatio n to determine the first time-out period. counter mode in counter mode, the timer counts input tr ansitions from a gpio port pin. the timer input is taken from the gpio po rt pin timer input alternate fu nction. the tpol bit in the timer control register selects whether the coun t occurs on the rising edge or the falling edge of the timer input signal. in c ounter mode, the prescaler is disabled. the input frequency of the timer input signal must not exceed on e-fourth the system clock frequency. further, the high or low stat e of the input signal pulse must be no less than twice the system clock period. a shorter pulse may not be captured. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is continuous mode time-out period (s) reload value prescale ? system clock frequency (hz) ------------------------------------------------------------------------ = caution:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 74 enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps for configuring a timer for counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for counter mode. ? select either the rising edge or falling edge of the timer input signal for the count. this selection also sets the initial logic level (high or low) for the timer output alternate function. ho wever, the timer output func tion is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode . after the first timer reload in coun- ter mode, counting always begins at the reset value of 0001h . in counter mode the timer high and low byte register s must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control re gister to enable the timer. ? in counter mode, the number of timer input transitions since the timer start is com- puted via the following equation: comparator counter mode in comparator counter mode, the timer co unts input transitions from the analog comparator output. the tpol bit in the timer control register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. in compar- ator counter mode, the prescaler is disabled. counter mode timer input tran sitions current count value - start value =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 75 the frequency of the comparator output sign al must not exceed on e-fourth the system clock frequency. further, the high or low state of the comparator output signal pulse must be no less than twice the system clock period. a shorter pulse may not be captured. after reaching the reload valu e stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. observe the following steps for config uring a timer for comparator counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for co mparator counter mode. ? select either the rising edge or falling edge of the comparator output signal for the count. this also sets the initial logic le vel (high or low) for the timer output alternate function. ho wever, the timer output func tion is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this action only affects the first pass in co mparator counter mode. after the first timer reload in comparator counter mode, counting always begins at the reset value of 0001h . generally, in comparator counter mode the timer high and low byte registers mu st be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control re gister to enable the timer. ? in comparator counter mode, the number of comparator output transitions since the timer start is computed via the following equation: caution: comparator output transitions current count value start value ? =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 76 pwm single output mode in pwm single output mode, the timer outputs a pulse-width modulator (pwm) output signal through a gpio port pin. the timer input is the system clock. the timer first counts up to the 16-bit pwm match value st ored in the timer pwm high and low byte registers. when the timer count value matche s the pwm value, the timer output toggles. the timer continues coun ting until it reaches the reload va lue stored in the timer reload high and low byte registers. upon reaching th e reload value, the timer generates an inter- rupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . observe the following steps for configur ing a timer for pwm single output mode and initiating the pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm single output mode ? set the prescale value ? set the initial logic level (high or low) and pwm high/low transition for the timer output alternate function ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always be gins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low byte registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. ?
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 77 the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equation to determine the first pwm time-out period. if tpol is set to 0, the ratio of the pwm outp ut high time to the total period is repre- sented by: if tpol is set to 1, the ratio of the pwm outp ut high time to the total period is repre- sented by: pwm dual output mode in pwm dual output mode, the timer ou tputs a pulse-width modulated (pwm) out- put signal pair (basic pwm signal and its complement) through two gpio port pins. the timer input is the system clock. the timer first counts up to the 16-bit pwm match value stored in the timer pwm high and low byte registers. when the timer count value matches the pwm value, the timer output t oggles. the timer con tinues counting until it reaches the reload value stored in the time r reload high and low byte registers. upon reaching the reload value, th e timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . the timer also generates a second pwm outp ut signal timer output complement. the timer output complement is the complement of the timer output pwm signal. a pro- grammable deadband delay can be configured to time delay (0 to 128 system clock cycles) pwm output transitions on these two pins from a low to a high (inactive to active). this pwm period (s) reload value prescale ? system clock frequency (hz) ------------------------------------------------------------------------ = pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------ 100 ? = pwm output high time ratio (%) pwm value reload value -------------------------------- 100 ? =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 78 delay ensures a time gap between the deassertion of one pwm output to the assertion of its complement. observe the following steps for configuring a timer for pwm dual output mode and initiating the pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm dual output mode by writing the tmode bits in the txctl1 register and the tmodehi bit in txctl0 register ? set the prescale value ? set the initial logic level (high or low) and pwm high/low transition for the timer output alternate function ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always be gins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the pwm control register to set the pwm dead band delay value. the dead- band delay must be less than the duration of the positive phase of the pwm signal (as defined by the pwm high and low byte registers). it must also be less than the dura- tion of the negative phase of the pwm sign al (as defined by the difference between the pwm registers and the timer reload registers). 5. write to the timer reload high and low byte registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 6. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 7. configure the associated gpio port pin fo r the timer output and timer output com- plement alternate functions. the timer outp ut complement functio n is shared with the timer input function for both timers. setting the timer mode to dual pwm auto- matically switches the function from timer in to timer out complement. 8. write to the timer control register to enable the timer and initiate counting. ? the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation determines the first pwm time-out period. pwm period (s) reload value x prescale system clock frequency (hz) ------------------------------------------------------------------------------- =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 79 if tpol is set to 0, the ratio of the pwm outp ut high time to the total period is repre- sented by: if tpol is set to 1, the ratio of the pwm outp ut high time to the total period is repre- sented by: capture mode in capture mode, the current timer count valu e is recorded when the appropriate exter- nal timer input transition occu rs. the capture count value is written to the timer pwm high and low byte registers. the timer input is the system clock. the tpol bit in the timer control register determines if the capt ure occurs on a rising edge or a falling edge of the timer input signal. when the capture ev ent occurs, an interrupt is generated and the timer continues counting. the inpcap bit in txctl0 regist er is set to indicate the timer interrupt is because of an input capture event. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching th e reload value, the timer generates an inter- rupt and continues counting. the inpcap b it in txctl0 register clears indicating the timer interrupt is not becaus e of an input capture event. observe the following steps for configuring a timer for capture mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . clearing these regis- ters allows the software to determine if interrupts were generated by either a capture event or a reload. if the pwm high an d low byte registers still contain 0000h after the interrupt, the interrupt was generated by a reload. pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------- 100 ? = pwm output high time ratio (%) pwm value reload value -------------------------------- 100 ? =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 80 5. enable the timer interrupt, if appropriate an d set the timer interrupt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events . if appropriate, configure th e timer interrupt to be gen- erated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: capture restart mode in capture restart mode, the current tim er count value is recorded when the acceptable external timer input transition oc curs. the capture count value is written to the timer pwm high and low byte registers. the timer input is th e system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture event oc curs, an interrupt is generated and the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txc tl0 register is set to indicate the timer interrupt is because of an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl0 register is cleared to indicate the timer interrupt is not cause d by an input capture event. observe the following steps for configuring a timer for capture restart mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture restar t mode by writing the tmode bits in the txctl1 register and the tmodehi bit in txctl0 register ? set the prescale value ? set the capture edge (rising or falling) for the timer input ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 81 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows the soft- ware to determine if interrupt s were generated by either a capture event or a reload. if the pwm high and low byte registers still contain 0000h after the interrupt, the interrupt was generated by a reload. 5. enable the timer interrupt, if appropriate an d set the timer interrupt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events . if appropriate, configure th e timer interrupt to be gen- erated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to the 16-bit maximu m compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and co unting continues (the timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) upon ? compare. if the timer reaches ffffh , the timer rolls over to 0000h and continue counting. observe the following steps for configuring a timer for compare mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for compare mode ? set the prescale value capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 82 ? set the initial logic level (high or low) fo r the timer output alternate function, if appropriate ? 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. ? in compare mode, the system clock always provides the timer input. the compare time can be calculated by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16-bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when r eaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal remains asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. observe the following steps for configuring a timer for gated mode and initiating the count: 1. write to the timer control register to: ? disable the timer compare mode time (s) compare value start value ? ?? prescale ? system clock frequency (hz) ----------------------------------------------------------------------------------------------------- =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 83 ? configure the timer for gated mode ? set the prescale value ? 2. write to the timer high and low byte registers to set the starting count value. writing these registers only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if appropriate an d set the timer interrupt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input deassertion and reload events. if appropri ate, configure the timer interrupt to be generated only at the input deassertion even t or the reload event by setting ticonfig field of the txctl0 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control re gister to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the acceptable transition (ri sing edge or falling edge) is set by the tpol bit in the timer control register. th e timer input is th e system clock. every subsequent acceptable transition (after the first) of the timer input signal captures the current count value. the capture valu e is written to the timer pwm high and low byte registers. when the capture event occurs, an interrupt is generated, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl0 register is set to indicat e the timer interrupt is caused by an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl0 register is cleared to indicate the timer interrupt is not because of an input capture event. observe the following steps for configurin g a timer for capture/compare mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture/compare mode ? set the prescale value
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 84 ? set the capture edge (rising or falling) for the timer input ? 2. write to the timer high and low byte regi sters to set the starting count value (typi- cally 0001h ). 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate an d set the timer interrupt priority by writing to the relevant interrupt registers.by defau lt, the timer interrupt are generated for both input capture and reload events . if appropriate, configure th e timer interrupt to be gen- erated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control re gister to enable the timer. 7. counting begins on the first appropriate tr ansition of the timer input signal. no inter- rupt is generated by this first edge. in capture/compare mode, the elapsed time from timer start to capture event can be calculated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when the timer is enabled and the timer high byte reg- ister is read, the contents of the timer low by te register are placed in a holding register. a subsequent read from the timer low byte re gister returns the valu e in the holding reg- ister. this operation allows accurate reads of the full 16-bit timer count value while enabled. when the timers are not enabled, a read from the timer low byte register returns the actual va lue in the counter. timer pin signal operation the timer output function is a gpio port pin alternate function. the timer output is tog- gled every time the counter is reloaded. capture elapsed time (s) capture value start value ? ?? prescale ? system clock frequency (hz) ---------------------------------------------------------------------------------------------------------------------- =
ps022827-1212 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f082a series product specification 85 the timer input can be used as a selectable counting source. it shares the same pin as the complementary timer output. when selected by the gpio alternate function registers, this pin functions as a timer input in all modes except for the dual pwm output mode. for this mode, there is no timer input available. timer control register definitions this section defines the features of the following timer control registers. timer 0?1 control registers : see page 85 timer 0?1 high and low byte registers : see page 89 timer reload high and low byte registers : see page 91 timer 0?1 pwm high and low byte registers : see page 92 timer 0?1 control registers the timer control registers are 8-bit read/write registers that control the operation of their associated counter/timers. time 0?1 control register 0 the timer control register 0 (txctl0) and timer control register 1 (txctl1), shown in table 50, determine the timer operating mode. these registers each include a program- mable pwm deadband delay, two bits to conf igure timer interrupt definition and a status bit to identify if the most recent timer in terrupt is caused by an input capture event. table 50. timer 0?1 control register 0 (txctl0) bit 7 6 5 4 3 2 1 0 field tmodehi ticonfig reserved pwmd inpcap reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/w r address f06h, f0eh bit description [7] ? tmodehi timer mode high bit this bit, along with the tmode field in th e txctl1 register, determines the operating mode of the timer. this bit is the most signif icant bit of the timer mo de selection value. see the description of the timer 0?1 control register 1 (txctl1) for details about the full timer mode decoding.
ps022827-1212 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f082a series product specification 86 timer 0?1 control register 1 the timer 0?1 control (txctl1) registers, shown in table 51, enable and disable the timers, set the prescaler value and determine the timer operating mode. [6:5] ? ticonfig timer interrupt configuration this field configures ti mer interrupt definition. 0x = timer interrupt occurs on all defined reload, compare and input events. ? 10 = timer interrupt only on defined input capture/deassertion events. ? 11 = timer interrupt only on defined reload/compare events. [4] reserved this bit is reserved and must be programmed to 0. [3:1] ? pwmd pwm delay value this field is a programmable delay to cont rol the number of system clock cycles delay before the timer output and th e timer output complement are forced to their active state. 000 = no delay. ? 001 = 2 cycles delay. ? 010 = 4 cycles delay. ? 011 = 8 cycles delay. ? 100 = 16 cycles delay. ? 101 = 32 cycles delay. ? 110 = 64 cycles delay. ? 111 = 128 cycles delay. [0] ? inpcap input capture event this bit indicates if the most recent timer in terrupt is caused by a timer input capture event. 0 = previous timer interrupt is not a result of timer input capture event. ? 1 = previous timer interrupt is a re sult of timer input capture event. table 51. timer 0?1 control register 1 (txctl1) bit 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f07h, f0fh bit description [7] ? ten timer enable 0 = timer is disabled. ? 1 = timer enabled to count. bit description (continued)
ps022827-1212 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f082a series product specification 87 [6] ? tpol timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output sig nal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented upon timer reload. continuous mode when the timer is disabled, the timer output sig nal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented upon timer reload. counter mode if the timer is enabled the timer output signal is complemented after timer reload. 0 = count occurs on the rising edge of the timer input signal. 1 = count occurs on the falling ed ge of the timer input signal. pwm single output mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer out- put is forced low (0) upon pwm count match and forced high (1) upon reload. capture mode 0 = count is captured on the rising edge of the timer input signal. ? 1 = count is captured on the fallin g edge of the time r input signal. compare mode when the timer is disabled, the timer output sig nal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented upon timer reload. bit description (continued)
ps022827-1212 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f082a series product specification 88 [6] ? tpol (cont?d) gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the timer input signal is low (0) and interrupts are generated on the rising edge of the timer input. capture/compare mode 0 = counting is started on the first rising edge of the timer input signal. the current count is captured on subsequent rising ed ges of the timer input signal. 1 = counting is started on the first falling edge of the timer input signal. the current count is captured on s ubsequent falling edges of the timer i nput signal. pwm dual output mode 0 = timer output is forced low (0) and timer output complement is forced high (1) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. when en abled, the timer output complement is forced low (0) upon pwm count match and forc ed high (1) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before the timer output and the timer outp ut complement is forced to high (1). 1 = timer output is forced high (1) and timer output complement is forced low (0) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload.when enabled, the timer output complement is forced high (1) upon pwm count match and fo rced low (0) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before the timer output and the timer ou tput complement is forced to low (0). capture restart mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the time r input signal. comparator counter mode when the timer is disabled, the timer output sig nal is set to the value of this bit. when the timer is enabled, the timer output signal is complemented upon timer reload. also: 0 = count is captured on the risi ng edge of the comparator output. 1 = count is captured on the fallin g edge of the comp arator output. ? caution: when the timer output alternate function txout on a gpio port pin is enabled, txout changes to whatever state the tpol bit is in.the timer does not need to be enabled for that to happen. also, the port data direction subr egister is not required to be set to output on txout. changing the tpol bit with the timer enabled and running does not immediately change the txout. bit description (continued)
ps022827-1212 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f082a series product specification 89 timer 0?1 high and low byte registers the timer 0?1 high and low byte (txh and txl) registers, shown in tables 52 and 53, contain the current 16-bit timer count value. when the timer is enabled, a read from txh causes the value in txl to be stored in a temporary holding register. a read from txl always returns this temporary register when the timers are enabled. when the timer is dis- abled, reads from txl read the register directly. writing to the timer high and low byte regist ers while the timer is enabled is not recom- mended. there are no temporary holding regist ers available for write operations, so simul- taneous 16-bit writes are not possible. if eith er the timer high or low byte registers are written during counting, the 8- bit written value is placed in the counter (high or low byte) at the next clock edge. the coun ter continues counting from the new value. [5:3] ? pres prescale value the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the prescaler is reset each time the timer is disabled. this rese t ensures proper clock division each time the timer is restarted. 000 = divide by 1. ? 001 = divide by 2. ? 010 = divide by 4. ? 011 = divide by 8. ? 100 = divide by 16. ? 101 = divide by 32. ? 110 = divide by 64. ? 111 = divide by 128. [2:0] ? tmode timer mode this field, along with the tmodehi bit in the txctl0 register, determine s the operating mode of the timer. tmodehi is the most significant bit of the timer mo de selection value. the entire operating mode bits are expre ssed as {tmodehi, tmod e[2:0]}. the tmodehi is bit 7 of the txctl0 register while tmode[2:0] is the lower 3 bits of the txctl1 register. 0000 = one-shot mode. ? 0001 = continuous mode. ? 0010 = counter mode. ? 0011 = pwm single output mode. ? 0100 = capture mode. ? 0101 = compare mode. ? 0110 = gated mode. ? 0111 = capture/compare mode. ? 1000 = pwm dual output mode. ? 1001 = capture restart mode. ? 1010 = comparator counter mode. bit description (continued)
ps022827-1212 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f082a series product specification 90 table 52. timer 0?1 high byte register (txh) bit 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f00h, f08h table 53. timer 0?1 low byte register (txl) bit 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f01h, f09h bit description [7:0] ? th, tl timer high and low bytes these 2 bytes, {th[7:0], tl[7:0]}, contain the current 16-bit timer count value.
ps022827-1212 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f082a series product specification 91 timer reload high and low byte registers the timer 0?1 reload high and low byte (txrh and txrl) registers, shown in tables 54 and 55, store a 16-bit reload value, {trh[7:0], trl[7:0]}. values written to the timer reload high byte register are stored in a temporary holding register. when a write to the timer reload low byte register occu rs, the temporary holding register value is written to the timer high byte register. this operation allows si multaneous updates of the 16-bit timer reload value. in compare mode, the timer reload high and low byte registers store the 16-bit compare value. table 54. timer 0?1 reload high byte register (txrh) bit 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f02h, f0ah table 55. timer 0?1 reload low byte register (txrl) bit 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f03h, f0bh bit description [7:0] ? trh, trl timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[7:0]}. this value sets the max- imum count value which init iates a timer reload to 0001h . in compare mode, these two bytes form the 16-bit compare value.
ps022827-1212 p r e l i m i n a r y timer control register definitions z8 encore! xp ? f082a series product specification 92 timer 0?1 pwm high and low byte registers the timer 0?1 pwm high and low byte (txpwmh and txpwml) registers, shown in tables 56 and 57, control pulse-width modula tor (pwm) operations. these registers also store the capture values for the capture and capture/compare modes. the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. table 56. timer 0?1 pwm high byte register (txpwmh) bit 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f04h, f0ch table 57. timer 0?1 pwm low byte register (txpwml) bit 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f05h, f0dh bit description [7:0] ? pwmh, pwml pulse-width modulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16 -bit value that is compared to the current 16-bit timer count. when a match occurs, t he pwm output changes state. the pwm output value is set by the tpol bit in the timer control re gister (txctl1) register.
ps022827-1212 p r e l i m i n a r y watchdog timer z8 encore! xp ? f082a series product specification 93 watchdog timer the watchdog timer (wdt) protects against co rrupt or unreliable so ftware, power faults and other system-level problems which ma y place the z8 encore! xp f082a series devices into unsuitable operating states. the features of watchdog timer include: ? on-chip rc oscillator ? a selectable time-out response: reset or interrupt ? 24-bit programmable time-out value operation the watchdog timer is a one-sh ot timer that resets or inte rrupts the z8 encore! xp f082a series devices when the wdt reaches its termin al count. the watchdog timer uses a ded- icated on-chip rc oscillator as its clock source. the watchdog timer operates in only two modes: on and off. once enabled, it always co unts and must be re freshed to prevent a time-out. perform an enable by executing th e wdt instruction or by setting the wdt_ao flash option bit. the wdt_ao bit forces th e watchdog timer to operate immediately upon reset, even if a wdt inst ruction has not been executed. the watchdog timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the ez8 cpu register space to set the reload value. the nominal wdt time-out period is described by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and the typical watchdog timer rc oscillator frequency is 10 khz. the watchdog ti mer cannot be refreshed after it reaches 000002h . the wdt reload value must no t be set to values below 000004h . table 58 provides infor- mation about approximate time-out delays for the minimum and maximum wdt reload values. table 58. watchdog timer approximate time-out delays wdt reload value (hex) wdt reload value (decimal) approximate time-out delay (with 10 khz typical wdt oscillator frequency) typical description 000004 4 400 ? s minimum time-out delay ffffff 16,777,215 28 minutes maximum time-out delay wdt time-out period (ms) wdt reload value 10 ------------------------------ ------------ =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 94 watchdog timer refresh when first enabled, the watchdog timer is loaded with the value in the watchdog timer reload registers. the watchdog timer counts down to 000000h unless a wdt instruc- tion is executed by the ez8 cpu. execution of the wdt instruction causes the downcoun- ter to be reloaded with th e wdt reload value stored in the watchdog timer reload registers. counting resumes fo llowing the reload operation. when the z8 encore! xp f082a series devices are operating in debug mode (using the on-chip debugger), the watchdog timer is co ntinuously refreshed to prevent any watch- dog timer time-outs. watchdog timer time-out response the watchdog timer times ou t when the counter reaches 000000h . a time-out of the watchdog timer generates either an interru pt or a system reset. the wdt_res flash option bit determines th e time-out response of the watchdog timer. for information about programming the wdt_res fl ash option bit, see the flash option bits chapter on page 159. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occu rs, the watchdog timer issues an interrupt request to the interrupt controller and sets the wdt status bit in the reset sta- tus (rststat) register; see the reset status register on page 29. if interrupts are enabled, the ez8 cpu responds to the inte rrupt request by fetching the watchdog timer interrupt vector and executing code from the ve ctor address. after time-out and interrupt generation, the watchdog timer counter rolls over to its maximum value of fffffh and continues counting. the watchdog timer coun ter is not automatically returned to its reload value. the reset status (rststat) register must be read before clearing the wdt interrupt. this read clears the wdt time-out flag an d prevents further wdt interrupts from imme- diately occurring. wdt interrupt in stop mode if configured to generate an interrupt when a time-out oc curs and the z8 encore! xp f082a series devices are in stop mode, the watchdog timer automatically initiates a stop mode recovery and generates an interrupt request. both the wdt status bit and the stop bit in the reset status (rststat) register are set to 1 following a wdt time-out in stop mode. for more informatio n about stop mode recovery, see the reset, stop mode recovery and low voltage detection chapter on page 22. if interrupts are enabled, following completi on of the stop mode recovery the ez8 cpu responds to the interrupt request by fetching the watchdog timer interrupt vector and exe- cuting code from the vector address.
ps022827-1212 p r e l i m i n a r y watchdog timer calibration z8 encore! xp ? f082a series product specification 95 wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the watchdog timer forces the device into the system reset state. the wd t status bit in the reset status (rststat) register is set to 1. for more in formation about system reset, see the reset, stop mode recovery and low voltage detection chapter on page 22. wdt reset in stop mode if configured to generate a reset when a time- out occurs and the device is in stop mode, the watchdog timer initiates a stop mode recovery. both the wdt status bit and the stop bit in the reset status (rststat) register are set to 1 following wdt time-out in stop mode. watchdog timer relo ad unlock sequence writing the unlock sequ ence to the watchdog timer (wdt ctl) control register address unlocks the three watchdog ti mer reload byte registers (wdtu, wdth and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload register s. observe the following steps to unlock the watchdog timer reload byte registers (wdtu, wdth and wdtl) for write access. 1. write 55h to the watchdog timer control register (wdtctl). 2. write aah to the watchdog timer control register (wdtctl). 3. write the watchdog timer reload upper byte register (wdtu) with the appropriate time-out value. 4. write the watchdog timer reload high by te register (wdth) with the appropriate time-out value. 5. write the watchdog timer reload low byte register (wdtl) with the appropriate time-out value. ? all three watchdog timer reload registers must be written in the order just listed. there must be no other register writes between each of these operations. if a register write occurs, the lock state machine resets and no further writes can occur unless the sequence is restarted. the value in the watchdog timer re load registers is loaded into the counter when the watchdog timer is first enabled and every time a wdt instruction is executed. watchdog timer calibration due to its extremely low oper ating current, the watchdog timer oscillator is somewhat inaccurate. this variation can be corrected us ing the calibration data stored in the flash information page; see tables 100 and 101 on page 173 for details. loading these values
ps022827-1212 p r e l i m i n a r y watchdog timer control register z8 encore! xp ? f082a series product specification 96 into the watchdog timer reload registers results in a one-second time-out at room tem- perature and 3.3 v supply voltage. time-outs other than one second may be obtained by scaling the calibration values up or down as required. the watchdog timer accuracy still degrades as temperature and supply voltage vary. see table 137 on page 235 for details. watchdog timer control register definitions this section defines the features of the fo llowing watchdog timer control registers. watchdog timer control register (wdtctl) : see page 96 watchdog timer reload upper byte register (wdtu) : see page 97 watchdog timer reload high byte register (wdth) : see page 97 watchdog timer reload lo w byte register (wdtl) : see page 98 watchdog timer control register the watchdog timer control (wdtctl) register is a write-only control register. writ- ing the 55h , aah unlock sequence to the wdtctl re gister address unlocks the three watchdog timer reload byte registers (wdt u, wdth and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register . the locking mechanism prevents spurious writes to the reload registers. this register address is shared with the read-only reset sta- tus register. table 59. watchdog timer control register (wdtctl) bit 7 6 5 4 3 2 1 0 field wdtunlk reset xxxxxxxx r/w wwwwwwww address ff0h note: x = undefined. bit description [7:0] ? wdtunlk watchdog timer unlock the software must write the correct unlocking se quence to this register before it is allowed to modify the contents of t he watchdog timer reload registers. note:
ps022827-1212 p r e l i m i n a r y watchdog timer control register z8 encore! xp ? f082a series product specification 97 watchdog timer reload upper, high and low byte registers the watchdog timer reload upper, high and low byte (wdtu, wdth, wdtl) regis- ters, shown in tables 60 through 62, form the 24-bit reload value that is loaded into the watchdog timer when a wdt instruction exec utes. the 24-bit reload value ranges across bits [23:0] to encompass the three bytes {wdtu[7:0], wdth[7:0], wdtl[7:0]}. writ- ing to these registers sets the appropriat e reload value. reading from these registers returns the current watchdog timer count value. the 24-bit wdt reload value must not be set to a value less than 000004h . table 60. watchdog timer reload upper byte register (wdtu) bit 7 6 5 4 3 2 1 0 field wdtu reset 00h r/w r/w* address ff1h note: a read returns the current wdt count val ue; a write sets the app ropriate reload value. bit description [7:0] ? wdtu wdt reload upper byte most-significant byte (msb); bits[23: 16] of the 24-bit wdt reload value. table 61. watchdog timer reload high byte register (wdth) bit 7 6 5 4 3 2 1 0 field wdth reset 04h r/w r/w* address ff2h note: a read returns the current wdt count value; a write sets the appropriate reload value. bit description [7:0] ? wdth wdt reload high byte middle byte; bits[15:8] of the 24-bit wdt reload value. caution:
ps022827-1212 p r e l i m i n a r y watchdog timer control register z8 encore! xp ? f082a series product specification 98 table 62. watchdog timer reload low byte register (wdtl) bit 7 6 5 4 3 2 1 0 field wdtl reset 00h r/w r/w* address ff3h note: a read returns the current wdt count value; a write sets the appropriate reload value. bit description [7:0] ? wdtl wdt reload low least significant byte (lsb), bits[7:0 ], of the 24-bit wdt reload value.
ps022827-1212 p r e l i m i n a r y universal asynchronous receiver/ z8 encore! xp ? f082a series product specification 99 universal asynchronous receiver/ transmitter the universal asynchronous re ceiver/transmitter (uart) is a full-duplex communication channel capable of handling asynchronous data transfers. the uart uses a single 8-bit data mode with selectable parity . features of the uart include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? option of one or two stop bits ? separate transmit and receive interrupts ? framing, parity, overrun and break detection ? separate transmit and receive enables ? 16-bit baud rate generator (brg) ? selectable multiprocessor (9-bit) mode with three configurable interrupt schemes ? baud rate generator (brg) can be conf igured and used as a basic 16-bit timer ? driver enable (de) output for external bus transceivers architecture the uart consists of three primary functional blocks: transmitter, rece iver and baud rate generator. the uart?s transmitter and receiv er function independently, but employ the same baud rate and data format. figur e 10 displays the uart architecture.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 100 operation the uart always transmits and receives data in an 8-bit data format, least-significant bit first. an even or odd parity bit can be added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figures 11 and 12 display the asynchronous data format employed by the uart without parity and with par- ity, respectively. figure 10. uart block diagram receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status register register register register baud rate generator de with address compare
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 101 transmitting data us ing the polled method observe the following steps to transmit da ta using the polled method of operation: 1. write to the uart baud rate high and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register, if multiprocessor mode is appropriate, to enable multiprocessor (9-bit) mode functions. 4. set the multiprocessor mode select ( mpen ) bit to enable multiprocessor mode. 5. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? set the parity enable bit ( pen ), if parity is appropriate and multiprocessor mode is not enabled and select either even or odd parity ( psel ) figure 11. uart asynchronous data format without parity figure 12. uart asynchronous data format with parity start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 102 ? set or clear the ctse bit to enable or disable control from the remote receiver using the cts pin ? 6. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 7 . if the transmit data register is full (indicated by a 0), continue to monitor the tdre bit until the transmit data register becomes ava ilable to receive new data. 7. write the uart control 1 register to select the outgoing address bit. 8. set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 9. write the data byte to the uart transm it data register. the transmitter automati- cally transfers the data to the transmit shift register and transmits the data. 10. make any changes to the multiprocessor bit transmitter ( mpbt ) value, if appropriate and multiprocessor mode is enabled. 11. to transmit additional bytes, return to step 5 . transmitting data using the interrupt-driven method the uart transmitter interrupt indicates the ava ilability of the transmit data register to accept new data for transmission. observe the following steps to configure the uart for interrupt-driven data transmission: 1. write to the uart baud rate high and low byte registers to set the appropriate baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the acceptable priority. 5. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if multiprocess or mode is appropriate. 6. set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 7. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? enable parity, if appropriate and if mu ltiprocessor mode is not enabled and select either even or odd parity
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 103 ? set or clear ctse to enable or disable control from the remote receiver using the cts pin ? 8. execute an ei instruc tion to enable interrupts. ? the uart is now configured for interrupt-d riven data transmission. because the uart transmit data register is empty, an interru pt is generated immediately. when the uart transmit interrupt is detected, the associated interrupt service routine (isr) performs the following: 1. write the uart control 1 register to select the multiprocessor bit for the byte to be transmitted: 2. set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 3. write the data byte to the uart transm it data register. the transmitter automati- cally transfers the data to the transmit shift register and transmits the data. 4. clear the uart transmit interrupt bit in the applicable interrupt request register. 5. execute the iret instruction to return from the interrupt-s ervice routine and wait for the transmit data register to again become empty. receiving data usin g the polled method observe the following steps to config ure the uart for polled data reception: 1. write to the uart baud rate high and low byte registers to set an acceptable baud rate for the incoming data stream. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiprocessor mode func- tions, if appropriate. 4. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multiprocessor mode is not enabled and select either even or odd parity. 5. check the rda bit in the uart status 0 register to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to step 5 . if the receive data register is empty (indicated by a 0), continue to monito r the rda bit awaiting reception of the valid data.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 104 6. read data from the uart receive data register. if operating in multiproces- sor (9-bit) mode, further actions may be required depending on the multipro- cessor mode bits mpmd[1:0]. 7. return to step 4 to receive additional data. receiving data using the interrupt-driven method the uart receiver interrupt indicates the availa bility of new data (a nd error conditions). observe the following steps to configure the uart receiver for interrupt-driven opera- tion: 1. write to the uart baud rate high and low byte registers to set the acceptable baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the acceptable priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9-bit) mode func- tions, if appropriate. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. ? set the multiprocessor mode bits, mpmd[1:0] , to select the acceptable address matching scheme. ? configure the uart to interrupt on received data and errors or errors only (inter- rupt on errors only is un likely to be useful for z8 encore! devices without a dma block) ? 7. write the device address to the address compare register (automatic multipro- cessor modes only). 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multip rocessor mode is not enabled and select either even or odd parity ? 9. execute an ei instruc tion to enable interrupt s.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 105 the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associat ed interrupt service routine (isr) performs the following: 1. checks the uart status 0 register to dete rmine the source of the interrupt - error, break, or received data. 2. reads the data from the uart receive data register if the interrupt was because of data available. if operating in multipro cessor (9-bit) mode, further actions may be required depending on the mult iprocessor mode bits mpmd[1:0]. 3. clears the uart receiver interrupt in th e applicable interrupt request register. 4. executes the iret instruction to return from the interrupt-service routine and await more data. clear to send ( cts ) operation the cts pin, if enabled by the ctse bit of the uart control 0 register, performs flow control on the outgoing transmit datastream. the clear to send (cts ) input pin is sam- pled one system clock before beginning any new character transmission. to delay trans- mission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data transm ission begins. for multiple character trans- missions, this action is typically perform ed during stop bit transmission. if cts deasserts in the middle of a character transmission, the current character is sent completely. multiprocessor (9-bit) mode the uart features a multiprocessor (9-bit) mode that uses an extra (9th) bit for selective communication when a number of processors share a common uart bus. in multiprocessor mode (also referred to as 9-bit mode ), the multiprocessor bit ( mp ) is transmitted immediately following the 8-bits of data and immediately preceding the stop bit(s) as displayed in figure 13. the character format is: figure 13. uart asynchronous multiprocessor mode data format start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 106 in multiprocessor (9-bit) mode, the parity (9th) bit location becomes the multipro- cessor control bit. the uart control 1 a nd status 1 registers provide multiproces- sor (9-bit) mode control and status inform ation. if an automatic address matching scheme is enabled, the uart address compare register hold s the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is enabled, the uart only processes frames addressed to it. the determination of whether a frame of data is addressed to the uart can be made in hardware, software or so me combination of the two, depending on the multiprocessor configuration bits. in general, the address co mpare feature reduces the load on the cpu, because it does not require access to the uart when it receives data directed to other devices on the multi-node ne twork. the following three multiprocessor modes are available in hardware: ? interrupt on all address bytes ? interrupt on matched address bytes and correctly framed data bytes ? interrupt only on corre ctly framed data bytes ? these modes are selected with mpmd[1:0] in the uart control 1 register. for all mul- tiprocessor modes, bit mpen of the uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0]. in this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. the interrupt service routine must manually check the addre ss byte that caused triggered the interrupt. if it matches the uart address, the software clears mpmd[0]. each new incoming byte interrupts the cpu. the software is responsib le for determining the end of the frame. it checks for the end-o f-frame by reading the mprx bit of the uart status 1 register for each incoming byte. if mprx =1, a new frame has begun. if the address of this new frame is different from the uart?s address, mpmd[0] must be set to 1 causing the uart inter- rupts to go inactive until the next address byte. if the new frame?s address matches the uart?s, the data in the new frame is processed as well. the second scheme requires th e following: set mpmd[1:0] to 10b and write the uart?s address into the uart address co mpare register. this mode introduces additional hard- ware control, interrupting only on frames that match the uart?s address. when an incoming address byte does no t match the uart?s address, it is ignored. all successive data bytes in this frame are also ignored. wh en a matching address byte occurs, an inter- rupt is issued and further inte rrupts now occur on each successi ve data byte. when the first data byte in the frame is read, the newfrm bit of the uart status 1 register is asserted. all successive data bytes have newfrm =0. when the next address byte occurs, the hard- ware compares it to the uart?s address. if there is a match, the interrupts continues and the newfrm bit is set for the first byte of the new frame. if there is no match, the uart ignores all incoming bytes un til the next address match.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 107 the third scheme is enable d by setting mpmd[1:0] to 11b and by writing the uart?s address into the uart address co mpare register. this mode is identical to the second scheme, except that there are no interrupts on address bytes. the first data byte of each frame remains accompanied by a newfrm assertion. external driver enable the uart provides a driver enable (de) si gnal for off-chip bus transceivers. this fea- ture reduces the software overhead associated with using a gpio pin to control the trans- ceiver when communicatin g on a multi-transceiver bus, such as rs-485. driver enable is an active high signal that envelopes the entire transmitted data frame including parity and stop bits as displayed in figure 14. the driver enable signal asserts when a byte is written to the uart transm it data register. the driver enable signal asserts at least one uart bit period and no greater than two uart bit periods before the start bit is transmitted. this allows a setup time to enable the transceiver. the driver enable signal deasserts one system clock period after the final stop bit is transmitted. this one system clock delay allows both time for da ta to clear the transc eiver before disabling it, plus the ability to determine if another ch aracter follows the current character. in the event of back to back characte rs (new data must be written to the transmit data register before the previous character is completely transmitted) the de signal is not deasserted between characters. the depol bit in the uar t control register 1 sets the polarity of the driver enable signal. the driver enable-to-start bit setup time is calculated as follows: figure 14. uart driver enable signal timing (shown with 1 stop bit and parity) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de 1 baud rate (hz) ---------------------------------------- - ?? ?? de to start bit setup time (s) 2 baud rate (hz) ---------------------------------------- - ?? ?? ??
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 108 uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disabled, the baud rate generator can also func- tion as a basic timer with interrupt capability. transmitter interrupts the transmitter generates a single interrupt when the transmit data register empty bit ( tdre ) is set to 1. this indicates that the tran smitter is ready to accept new data for trans- mission. the tdre interrupt occurs after the transmit shift register has shifted the first bit of data out. the transmit data register can now be written with the next character to send. this action provides 7 bit periods of la tency to load the transmit data register before the transmit shift regist er completes shifting the current character. writing to the uart transmit data register clears the tdre bit to 0. receiver interrupts the receiver generates an interrupt wh en any of the following actions occur: ? a data byte is received and is available in the uart receive data register. this inter- rupt can be disabled independently of the other receiver interrupt sources. the received data interrupt occurs after the receive character has been received and placed in the re- ceive data register. to avoid an overrun erro r, software must respond to this received data available condition before the next character is completely received. in multiprocessor mode ( mpen = 1 ), the receive data interru pts are dependent on the multiprocessor configuration and the most recent address byte. ? a break is received. ? an overrun is detected. ? a data framing error is detected. uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been read, the uart st atus 0 register is updated to indicate the overrun condition (and break detect, if applicable). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error occurred, this byte may not contain valid da ta and must be ignored. the brkd bit indi- cates if the overrun was caused by a break condition on the line. after reading the status note:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 109 byte indicating an overrun error, the receive data register must be read again to clear the error bits is the uart status 0 register. upda tes to the receive data register occur only when the next data word is received. uart data and error handling procedure figure 15 displays the recommended procedur e for use in uart receiver interrupt service routines. baud rate gene rator interrupts if the baud rate generator (brg) interrupt enable is set, the uart receiver interrupt asserts when the uart baud rate generator reloads. this conditio n allows the baud figure 15. uart receiver in terrupt service routine flow receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 110 rate generator to function as an additional counter if the uart functionality is not employed. uart baud ra te generator the uart baud rate generator creates a lowe r frequency baud rate clock for data trans- mission. the input to the baud rate generator is the system clock. the uart baud rate high and low byte registers combine to cr eate a 16-bit baud rate divisor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated usin g the following equation: when the uart is disabled, the baud rate generator functions as a basic 16-bit timer with an interrupt upon time-ou t. observe the following step s to configure the baud rate generator as a timer with an interrupt upon time-out: 1. disable the uart by clearing the ren and ten bits in the uart control 0 register to 0. 2. load the acceptable 16-bit count value into the uart ba ud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the brgctl bit in the uart control 1 register to 1. ? when configured as a general purpose timer, th e interrupt interval is calculated using the following equation: uart control register definitions the uart control registers support the uart and the associated infrared encoder/ decoders. for more information about infrared operation, see the infrared encoder/ decoder chapter on page 120. uart control 0 and control 1 registers the uart control 0 (uxctl0) and control 1 (uxctl1) registers, shown in tables 63 and 64, configure the properties of the uart?s transmit and receive operations. the uart control registers must not be written while the uart is enabled. uart data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ? -------------------------------------------------------------------------------- - = interrupt interval s ?? system clock period (s) brg 15:0 ?? ? =
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 111 table 63. uart control 0 register (u0ctl0) bit 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f42h bit description [7] ? ten transmit enable this bit enables or disables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. ? 0 = transmitter disabled. ? 1 = transmitter enabled. [6] ? ren receive enable this bit enables or disables the receiver. ? 0 = receiver disabled. ? 1 = receiver enabled. [5] ? ctse cts enable 0 = the cts signal has no effect on the transmitter. ? 1 = the uart recognizes the cts signal as an enable control from the transmitter. [4] ? pen parity enable this bit enables or disables parity. ev en or odd is determined by the psel bit. ? 0 = parity is disabled. ? 1 = the transmitter sends data with an additional parity bit and the receiver receives an addi- tional parity bit. [3] ? psel parity select 0 = even parity is transmitted and expected on all received data. ? 1 = odd parity is transmitted and expected on all received data. [2] ? sbrk send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so ensure that the transmitter has fi nished sending data before setting this bit. ? 0 = no break is sent. ? 1 = forces a break condition by setting the output of the transmitter to zero. [1] ? stop stop bit select 0 = the transmitter sends one stop bit. ? 1 = the transmitter sends two stop bits. [0] ? lben loop back enable 0 = normal operation. ? 1 = all transmitted data is lo oped back to the receiver.
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 112 table 64. uart control 1 register (u0ctl1) bit 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f43h bit description [7,5] ? mpmd[1,0] multiprocessor mode if multiprocessor (9-b it) mode is enabled: 00 = the uart generates an interrupt request on all received bytes (data and address). 01 = the uart generates an interrupt request only on received address bytes. 10 = the uart generates an interrupt request when a received address byte matches the value stored in the address compare register and on all successive data bytes until an address mismatch occurs. 11 = the uart generates an interrupt request on all received data bytes for which the most recent address byte matched the val ue in the address compare register. [6] ? mpen multiprocessor (9-bit) enable this bit is used to enable multiprocessor (9-bit) mode. ? 0 = disable multiprocessor (9-bit) mode. ? 1 = enable multiprocessor (9-bit) mode. [4] ? mpbt multiprocessor bit transmit this bit is applicable only when multiprocesso r (9-bit) mode is enabled. the 9th bit is used by the receiving device to determine if the data byte contains address or data informa- tion. ? 0 = send a 0 in the multiprocessor bit location of the data stream (data byte). ? 1 = send a 1 in the multiprocessor bit location of the data stream (address byte). [3] ? depol driver enable polarity 0 = de signal is active high. ? 1 = de signal is active low.
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 113 [2] ? brgctl baud rate control this bit causes an alternate uart behavior dep ending on the value of the ren bit in the uart control 0 register. when the uart receiv er is not enabled (ren=0), this bit deter- mines whether the baud rate generator issues interrupts. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = the baud rate generator generates a receive interrupt when it counts down to 0. reads from the baud rate high and low byte registers return the current brg count value. when the uart receiver is enabled (ren=1), this bit allows reads from the baud rate reg- isters to return the brg count value instead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and low byte registers return the current brg count value. unlike the timers, there is no mech anism to latch the low byte when the high byte is read. [1] ? rdairq receive data interrupt enable 0 = received data and receiver errors generates an interrupt request to the interrupt con- troller. 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. [0] ? iren infrared encoder/decoder enable 0 = infrared encoder/decoder is disabled. uart operates normally. 1 = infrared encoder/decoder is enabled. the uart transmits and receives data through the infrared encoder/decoder. bit description (continued)
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 114 uart status 0 register the uart status 0 (uxstat0) and status 1(ux stat1) registers, shown in tables 65 and 66, identify the current uart oper ating configuration and status. table 65. uart status 0 register (u0stat0) bit 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 0000011x r/w rrrrrrrr address f41h bit description [7] ? rda receive data available this bit indicates that the uart receive data register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty. 1 = there is a byte in the uart receive data register. [6] ? pe parity error this bit indicates that a parity error has occu rred. reading the uart receive data register clears this bit. 0 = no parity error has occurred. 1 = a parity error has occurred. [5] ? oe overrun error this bit indicates that an overrun error has occurred. an overrun occurs when new data is received and the uart receive data register has not been read. if the rda bit is reset to 0, reading the uart receive data register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. [4] ? fe framing error this bit indicates that a framing error (no st op bit following data reception) was detected. reading the uart receive data register clears this bit. 0 = no framing error occurred. ? 1 = a framing error occurred. [3] ? brkd break detect this bit indicates that a break occurred. if the da ta bits, parity/multiprocessor bit and stop bit(s) are all 0s this bit is set to 1. reading th e uart receive data register clears this bit. 0 = no break occurred. ? 1 = a break occurred.
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 115 uart status 1 register this register contains multipro cessor control and status bits. uart transmit data register data bytes written to the uart transmit data (uxtxd) register, shown in table 67, are shifted out on the txdx pin. the write-only uart transmit data register shares a reg- ister file address with the read -only uart receive data register. [2] ? tdre tdre?transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit da ta register resets this bit. 0 = do not write to the uart transmit data register. 1 = the uart transmit data register is ready to receive an additional byte to be transmitted. [1] ? txe transmitter empty this bit indicates that the transmit shift register is empty and character transmission is finished. 0 = data is curren tly transmitting. 1 = transmission is complete. [0] ? cts cts signal when this bit is read it returns the level of the cts signal. this signal is active low. table 66. uart status 1 register (u0stat1) bit 7 6 5 4 3 2 1 0 field reserved newfrm mprx reset 00000000 r/w rrrrr/wr/wrr address f44h bit description [7:2] reserved these bits are reserved and must be programmed to 000000. [1] ? newfrm new frame a status bit denoting the start of a new frame. reading the uart receive data register resets this bit to 0. ? 0 = the current byte is not the first data byte of a new frame. ? 1 = the current byte is the first data byte of a new frame. [0] ? mprx multiprocessor receive returns the value of the most recent multip rocessor bit received. reading from the uart receive data register resets this bit to 0. bit description (continued)
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 116 uart receive data register data bytes received through the rxd x pin are stored in the uart receive data (uxrxd) register, shown in table 68. the read-only uart receive data register shares a register file address with the write-only uart transmit data register. uart address compare register the uart address compare (uxaddr) regist er stores the multi-node network address of the uart (see table 69). when the mpmd[1 ] bit of uart control register 0 is set, all incoming address bytes are compared to the value stored in the address compare reg- ister. receive interrupts and rda assertions only occur in the event of a match. table 67. uart transmit data register (u0txd) bit 7 6 5 4 3 2 1 0 field txd reset xxxxxxxx r/w wwwwwwww address f40h note: x = undefined. bit description [7:0] ? txd transmit data uart transmitter data byte to be shifted out through the txd x pin. table 68. uart receive data register (u0rxd) bit 7 6 5 4 3 2 1 0 field rxd reset xxxxxxxx r/w rrrrrrrr address f40h note: x = undefined. bit description [7:0] ? rxd receive data uart receiver data byte from the rxd x pin.
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 117 uart baud rate high and low byte registers the uart baud rate high (uxbrh) and low byte (uxbrl) registers, shown in tables 70 and 71, combine to create a 16-bit baud rate divisor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. table 69. uart address co mpare register (u0addr) bit 7 6 5 4 3 2 1 0 field comp_addr reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f45h bit description [7:0] ? comp_addr compare address this 8-bit value is compared to incoming address bytes. table 70. uart baud rate hi gh byte register (u0brh) bit 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f46h bit description [7:0] ? brh uart baud rate high byte table 71. uart baud rate low byte register (u0brl) bit 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f47h bit description [7:0] ? brl uart baud rate low byte
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 118 the uart data rate is calcula ted using the following equation: for a given uart data rate, calcu late the integer baud rate di visor value using the follow- ing equation: the baud rate error relative to the acceptable baud rate is calculated usin g the following equation: for reliable communication, the uart baud ra te error must never exceed 5 percent. table 72 provides information about the data rate errors for popula r baud rates and com- monly used crystal oscillator frequencies. table 72. uart baud rates 10.0 mhz system clock 5.5296 mhz system clock acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 1 625.0 0.00 625.0 n/a n/a n/a 250.0 3 208.33 ?16.67 250.0 1 345.6 38.24 115.2 5 125.0 8.51 115.2 3 115.2 0.00 57.6 11 56.8 ?1.36 57.6 6 57.6 0.00 38.4 16 39.1 1.73 38.4 9 38.4 0.00 19.2 33 18.9 0.16 19.2 18 19.2 0.00 9.60 65 9.62 0.16 9.60 36 9.60 0.00 4.80 130 4.81 0.16 4.80 72 4.80 0.00 2.40 260 2.40 ?0.03 2.40 144 2.40 0.00 1.20 521 1.20 ?0.03 1.20 288 1.20 0.00 0.60 1042 0.60 ?0.03 0.60 576 0.60 0.00 0.30 2083 0.30 0.2 0.30 1152 0.30 0.00 3.579545 mhz system clock 1.8432 mhz system clock uart baud rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ? ----------------------------------------------------------------------------------------------- - = uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) ? ------------------------------------------------------------------------------- ?? ?? = uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate ---------------------------------------------------------------------------------------------------- ?? ?? ? =
ps022827-1212 p r e l i m i n a r y uart control register definitions z8 encore! xp ? f082a series product specification 119 acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 223.72 ?10.51 250.0 n/a n/a n/a 115.2 2 111.9 ?2.90 115.2 1 115.2 0.00 57.6 4 55.9 ?2.90 57.6 2 57.6 0.00 38.4 6 37.3 ?2.90 38.4 3 38.4 0.00 19.2 12 18.6 ?2.90 19.2 6 19.2 0.00 9.60 23 9.73 1.32 9.60 12 9.60 0.00 4.80 47 4.76 ?0.83 4.80 24 4.80 0.00 2.40 93 2.41 0.23 2.40 48 2.40 0.00 1.20 186 1.20 0.23 1.20 96 1.20 0.00 0.60 373 0.60 ?0.04 0.60 192 0.60 0.00 0.30 746 0.30 ?0.04 0.30 384 0.30 0.00 table 72. uart baud rates (continued)
ps022827-1212 p r e l i m i n a r y infrared encoder/decoder z8 encore! xp ? f082a series product specification 120 infrared encoder/decoder z8 encore! xp f082a series products cont ain a fully-functional, high-performance uart to infrared encoder/decode r (endec). the infrared endec is integrated with an on- chip uart to allow easy co mmunication between the z8 encore! xp mcu and irda physical layer specification, version 1.3-compliant infrare d transceivers. infrared com- munication provides secure, reliable, low-co st, point-to-point co mmunication between pcs, pdas, cell phones, printers and other infrared enabled devices. architecture figure 16 displays the architecture of the infrared endec. operation when the infrared endec is enabled, the tr ansmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infra- red transceiver through the txd pin. likewise, data received from the infrared transceiver is passed to the infrared endec through the rxd pin, decoded by the infrared endec and passed to the uart. communication is hal f-duplex, which means simultaneous data transmission and reception is not allowed. figure 16. infrared data communication system block diagram interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data infrared transceiver rxd txd baud rate clock (endec)
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 121 the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enabled to use the infrared endec. the infrared endec data rate is calculated us ing the following equation: transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16 clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16 clock period. if the data to be transmitted is 0, the transmitter first out- puts a 7 clock low period, followed by a 3 clock high pulse. finally, a 6 clock low pulse is output to complete the full 16 clock data pe riod. figure 17 displays irda data transmis- sion. when the infrared endec is enabled, th e uart?s txd signal is internal to the z8 encore! xp f082a series products while the ir_txd signal is output through the txd pin. figure 17. infrared data transmission infrared data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ? ------------------- ------------------------------------------ ------------------- - = baud rate ir_txd uart?s 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3 clock pulse txd clock
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 122 receiving irda data data received from the infrare d transceiver using the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate the demodulated si gnal (rxd) that drives the uart. each uart/infrared data bit is 16-clock s wide. figure 18 displays data reception. when the infrared endec is enab led, the uart?s rxd signal is internal to the z8 encore! xp f082a series products while the ir_rxd signal is received through the rxd pin. infrared data reception the system clock frequency must be at least 1.0 mhz to ensure proper reception of the 1.4 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is rese t. when the count reac hes a value of 8, the uart rxd value is updated to reflect the va lue of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. figure 18. irda data reception baud rate uart?s ir_rxd 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8 clock delay clock rxd 16 clock period 16 clock period 16 clock period 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.4 ? s pulse caution:
ps022827-1212 p r e l i m i n a r y infrared encoder/decoder control register z8 encore! xp ? f082a series product specification 123 the window remains open until th e count again reaches 8 (that is, 24 baud clock periods since the previous pulse was detected), giving the endec a sampling window of minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. if an incoming pulse is detected inside this window th is process is repeated. if the incoming data is a logical 1 (no pulse), the endec returns to the in itial state and waits for the next falling edge. as each falling edge is detected, the endec clock counter is reset, resynchronizing the endec to th e incoming signal, allowing th e endec to tolerate jitter and baud rate errors in the incoming datastream . resynchronizing the endec does not alter the operation of the uart, which ultimately re ceives the data. the uart is only synchro- nized to the incoming data str eam when a start bit is received. infrared encoder/decoder co ntrol register definitions all infrared endec configuration and status in formation is set by the uart control regis- ters as defined in the universal asynchronous receiver/transmitter section on page 99. to prevent spurious signals during irda data transmission, set the iren bit in the uart control 1 register to 1 to enable the infra red encoder/decoder befo re enabling the gpio port alternate function for the corresponding pin. caution:
ps022827-1212 p r e l i m i n a r y analog-to-digital converter z8 encore! xp ? f082a series product specification 124 analog-to-digital converter the analog-to-digital converter (adc) converts an analog input signal to its digital repre- sentation. the features of th is sigma-delta adc include: ? 11-bit resolution in differential mode ? 10-bit resolution in single-ended mode ? eight single-ended analog input sources are multiplexed with general-purpose i/o ports ? 9 th analog input obtained from temperature sensor peripheral ? 11 pairs of differential inputs also mu ltiplexed with general-purpose i/o ports ? low-power operational amplifier (lpo) ? interrupt on conversion complete ? bandgap generated internal voltage reference with two selectable levels ? manual in-circuit calibration is possible employing user code (offset calibration) ? factory calibrated for in-c ircuit error compensation architecture figure 19 displays the major functional bl ocks of the adc. an analog multiplexer net- work selects the adc inpu t from the available analog pins, ana0 through ana7. the input stage of the adc allows both di fferential gain and buffering. the following input options are available: ? unbuffered input (single-en ded and differential modes) ? buffered input with unity gain (s ingle-ended and differential modes) ? lpo output with full pin access to the feedback path
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 125 operation in both single-ended and differential modes, the effective output of the adc is an 11-bit, signed, two?s complement digita l value. in differential mode, the adc can output values across the entire 11-bit range, from ?1024 to +1023. in single- ended mode, the output generally ranges from 0 to +1023, but offset errors can cause small negative values. figure 19. analog-to-digital converter block diagram temp analog input multiplexer internal voltage reference generator analog in + ref input sensor analog in - + - v ref pin adc irq adc data 13 bit sigma-delta adc v refsel 2 13 analog input multiplexer ana7 ana6 ana5 ana4 ana3 ana2 ana1 ana0 ana5 ana4 ana3 ana2 ana1 ana0 f or offset calibration anain 4 buffer amplifier + - low-power operational amplifier buffmode vrefext amplifier tristates when disabled
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 126 the adc registers actually return 13 bits of data, but the two lsbs are intended for com- pensation use only. when the software compensation routine is performed on the 13 bit raw adc value, two bits of reso lution are lost because of a rounding error. as a result, the final value is an 11-bit number. hardware overflow when the hardware overflow bit (ovf) is set in adc data low byte (adcd_l) regis- ter, all other data bits are in valid. the hardware overflow bit is set for values greater than v ref and less than ?v ref (differential mode). automatic powerdown if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powe red down. from this powerdown state, the adc requires 40 system clock cycles to power up. the adc powers up when a conver- sion is requested by the adc control register. single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. observe the following step s for setting up the adc and initiating a sin- gle-shot conversion: 1. enable the appropriate analog inputs by co nfiguring the general-purpose i/o pins for alternate analog function. this configura tion disables the digital input and output drivers. 2. write the adc control/status register 1 to configure the adc. ? write to bufmode[2:0] to select single-ended or differential mode, plus unbuffered or buffered mode. ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refsell bit is. contained in the adc control register 0. ? 3. write to the adc control register 0 to configure the adc and begin the conversion. the bit fields in the adc control register can be written simultaneously (the adc can be configured and enabled w ith the same write instruction): ? write to the anain[3:0] field to select from the avai lable analog input sources (different input pins available depending on the device). ? clear cont to 0 to select a single-shot conversion.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 127 ? if the internal voltage reference mu st be output to a pin, set the refext bit to 1. the internal voltage reference must be enabled in this case. ? write the refsell bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refselh bit is contained in the adc co ntrol/status register 1. ? set cen to 1 to start the conversion. ? 4. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered down state, the adc uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion. 5. when the conversion is co mplete, the adc control logi c performs the following oper- ations: ? 13-bit two?s-complement result wr itten to {adcd_h[7:0], adcd_l[7:3]} ? sends an interrupt request to the interrupt controlle r denoting conversion com- plete ? cen resets to 0 to indicate the conversion is complete ? 6. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered down. continuous conversion when configured for continuous conversion , the adc continuously performs an analog- to-digital conversion on the selected analog input. each new data value overwrites the pre- vious value stored in the adc data registers. an interrupt is generated after each conver- sion. in continuous mode, adc updates are limited by the input signal bandwidth of the adc and the latency of the adc and its digital filter. step changes at the input are not immediately detected at the next output fro m the adc. the response of the adc (in all modes) is limited by the input signal bandwidth and the latency. observe the following steps fo r setting up the adc and initia ting continuous conversion: 1. enable the appropriate analog input by configuring the general-purpose i/o pins for alternate function. this action disables the digital input and output driver. 2. write the adc control/status register 1 to configure the adc. caution:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 128 ? write to bufmode [2:0] to select single-ended or differential mode, plus unbuffered or buffered mode. ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refsell bit is contained in the adc control register 0. ? 3. write to the adc control register 0 to co nfigure the adc for continuous conversion. the bit fields in the adc control re gister may be written simultaneously: ? write to the anain[3:0] field to select from the avai lable analog input sources (different input pins available depending on the device). ? set cont to 1 to select continuous conversion. ? if the internal vref must be output to a pin, set the refext bit to 1. the internal voltage reference must be enabled in this case. ? write the refsell bit of the pair { refselh, refsell } to select the internal voltage reference level or to disa ble the internal reference. the refselh bit is contained in adc control/status register 1. ? set cen to 1 to start the conversions. ? 4. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation ? an interrupt request is sent to the interru pt controller to indicate the conversion is complete ? 5. the adc writes a new data result every 256 system clock cycles. for each completed conversion, the adc control logic performs the following operations: ? writes the 13-bit two?s complement r esult to {adcd_h[7:0], adcd_l[7:3]} ? sends an interrupt request to the interrupt controlle r denoting conversion com- plete ? 6. to disable continuous conversion, clear the cont bit in the adc control register to 0. interrupts the adc is able to interrupt the cpu when a conversion has been completed. when the adc is disabled, no new interrupts are asserted; however, an interrupt pending when the adc is disabled is not cleared.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 129 calibration and compensation the z8 encore! xp f082a series adc is factor y calibrated for offset error and gain error, with the compensation data stored in flash memory. alternatively, you can perform your own calibration, storing the values into flash themselves. thirdly, the user code can per- form a manual offset calibration during differential mode operation. factory calibration devices that have been factory calibrated cont ain 30 bytes of calibration data in the flash option bit space. this data cons ists of 3 bytes for each inpu t mode, one for offset and two for gain correction. for a lis t of input modes for which ca libration data exists, see the zilog calibration data section on page 168. user calibration if you have precision references available, its own external calibration can be performed using any input modes. this calibration data takes into account buff er offset and nonlin- earity; therefore zilog recommends that this ca libration be performed separately for each of the adc input modes planned for use. manual offset calibration when uncalibrated, the adc has significant offset (see table 139 on page 236). subse- quently, manual offset calibration capability is built into th e block. when the adc con- trol register 0 sets the input mode ( anain[2:0] ) to manual offset calibration mode, the differential inputs to th e adc are shorted together by an inter- nal switch. reading the adc value at this po int produces 0 in an id eal system. the value actually read is the adc offset . this value can be stored in nonvolatile memory (see the nonvolatile data storage chapter on page 176) and accessed by user code to compensate for the input offset error. there is no provision for manual gain calibration. software compensation procedure using factory calibration data the value read from the adc high and low by te registers is uncompensated. the user mode software must apply gain and offset correction to this un compensated value for maximum accuracy. the following equa tion yields the compensated value: where gaincal is the gain calibration value, offcal is the offset calibration value and adc uncomp is the uncompensated value read from the adc. all values are in two?s com- plement format. adc comp adc uncomp offcal ? ?? adc uncomp offcal ? ?? gaincal ? ?? 2 16 ? + =
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 130 the offset compensation is perfo rmed first, followed by the ga in compensation. one bit of resolution is lost because of rounding on bo th the offset and gain computations. as a result the adc registers read back 13 bits: 1 si gn bit, two calibration b its lost to rounding and 10 data bits. ? ? also note that in the second term, the multiplication must be performed before the divi- sion by 2 16 . otherwise, the second term incorrectly evaluates to zero. although the adc can be used without the gain and offset compensation, it does exhibit nonunity gain. designing the adc with su b-unity gain reduces noise across the adc range but requires the adc results to be scaled by a factor of 8/7. adc compensation details high-efficiency assembly code that perform s adc compensation is available for down- load on w ww.zilog.com . this section offers a bit-specific description of the adc compen- sation process used by this code. the following data bit definitions are used: 0?9, a?f = bit indices in hexadecimal ? s = sign bit? v = overflow bit ? ? = unused input data msb lsb s b a 9 8 7 6 5 4 3 2 1 0 ? ? v (adc) adc output word; if v = 1, the data is invalid s 6 5 4 3 2 1 0 offset correction byte s s s s s 7 6 5 4 3 2 1 0 0 0 0 (offset) offset byte shifted to align with adc data s e d c b a 9 8 7 6 5 4 3 2 1 0 (gain) gain correction word note: caution:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 131 compensation steps: 1. correct for offset: ? = 2. compute the absolute value of the offset-corrected adc value if negative ; the gain correction factor is computed assuming posi tive numbers, with sign restoration after- ward. also compute the absolute value of the gain correction word, if negative. 3. multiply by the gain correction word. if operating in differential mode, there are two gain correction values: one for positive adc values, another for negative adc values. use the appropriate gain corr ection word based on the sign computed by byte #2. * = adc msb adc lsb offset msb offset lsb #1 msb #1 lsb #2 msb #2 lsb again msb again lsb #2 msb #2 lsb again msb again lsb
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 132 4. round the result and discard the least significant two by tes (equivalent to dividing by 2 16 ). ? = 5. determine the sign of the gain correc tion factor using the sign bits from step 2 . if the offset-corrected adc value and the gain correction word both have the same sign, then the factor is positive and remains unch anged. if they have differing signs, then the factor is negative and must be multiplied by ?1. 6. add the gain correction factor to the original offset corrected value. + = 7. shift the result to the right, using the sign bit determined in step 1 , to allow for the detection of computational overflow. #3 #3 #3 #3 #3 #3 #3 #3 0x00 0x00 0x80 0x00 #4 msb #4 lsb #5 msb #5 lsb #5 msb #5 lsb #1 msb #1 lsb #6 msb #6 lsb s #6 msb #6 lsb
ps022827-1212 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f082a series product specification 133 output data the output format of the corrected adc value is shown below. the overflow bit in the corrected output in dicates that the computed value was greater than the maximum logical value (+1023) or less than the minimum logical value (?1024). unlike the hardware overflow b it, this is not a simple binary flag. for a normal (nonover- flow) sample, the sign and the overflow bit match. if the sign bit and overflow bit do not match, a computational overflow has occurred. input buffer stage many applications require the measurement of an input voltage source with a high output impedance. this adc provides a buffered inpu t for such situations. the drawback of the buffered input is a limitation of the input rang e. when using unity gain buffered mode, the input signal must be prevented fro m coming too close to either v ss or v dd . see table 139 on page 236 for details. this condition applie s only to the input voltage level (w ith respect to ground) of each dif- ferential input signal. the act ual differential input voltage magnitude may be less than 300 mv. the input range of the unbuffered adc swings from v ss to v dd . input signals smaller than 300 mv must use the unbuffered input mode. if these signals do not contain low out- put impedances, they might require off-chip buffering. signals outside the allowable input range can be used without instability or device dam- age. any adc readings made outside the input range are su bject to greater inaccuracy than specified. adc control register definitions this section defines the features of the following adc control registers. adc control register 0 (adcctl0) : see page 134 adc control/status register 1 (adcctl1) : see page 136 adc data high byte register (adcd_h) : see page 137 adc data low byte register (adcd_l) : see page 137 msb lsb s v b a 9 8 7 6 5 4 3 2 1 0 ? ?
ps022827-1212 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f082a series product specification 134 adc control register 0 the adc control register 0 (adcctl0) sel ects the analog input channel and initiates the analog-to-digital conversion. it also se lects the voltage refe rence configuration. table 73. adc control register 0 (adcctl0) bit 7 6 5 4 3 2 1 0 field cen refsell refout cont anain[3:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f70h bit description [7] ? cen conversion enable 0 = conversion is complete. writing a 0 produces no effect. the adc automatically clears this bit to 0 when a conversion is complete. 1 = begin conversion. writing a 1 to this bit star ts a conversion. if a conversion is already in progress, the conversion restarts. this bit remains 1 until the conversion is complete. [6] ? refsell voltage reference level select low bit in conjunction with the high bit (refselh) in adc control/status regi ster 1, this deter- mines the level of the internal voltage refere nce; the following details the effects of {ref- selh, refsell}; note that this reference is independent of the comparator reference. 00 = internal reference disabled, reference comes from external pin. ? 01 = internal reference set to 1.0 v. ? 10 = internal reference set to 2.0 v (default). ? 11 = reserved. [5] ? refout internal reference output enable 0 = reference buffer is disabled; vref pin is available for gpio or analog functions. 1 = the internal adc reference is buffered and driven out to the v ref pin. caution: when the adc is used with an external reference ({refselh,refsell}=00), the refout bit must be set to 0. [4] ? cont conversion 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles (measurements of the internal te mperature sensor take twice as long). 1 = continuous conversion. adc data updated ev ery 256 system clock cycles after an initial 5129 clock conversion (measurements of the internal temperature sensor take twice as long). [3:0] ? anain[3:0] analog input select these bits select the analog input for conversion. not all port pins in this list are available in all packages for the z8 encore! xp f082a series. for information about port pins available with each package style, see the pin description chapter on page 8. do not enable unavail- able analog inputs. usage of these bits changes depending on the buffer mode selected in adc control/status register 1.
ps022827-1212 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f082a series product specification 135 for the reserved values, all inpu t switches are disabled to avoid leakage or other undesir- able operation. adc samples taken with reserved bit settings are undefined. single-ended mode: 0000 = ana0 (transimpedance amp output when enabled) ? 0001 = ana1 (transimpedance amp inverting input) ? 0010 = ana2 (transimpedance amp noninverting input) ? 0011 = ana3 ? 0100 = ana4 ? 0101 = ana5 ? 0110 = ana6 ? 0111 = ana7 ? 1000 = reserved ? 1001 = reserved ? 1010 = reserved ? 1011 = reserved ? 1100 = hold transimpedance input nodes (ana1 and ana2) to ground. ? 1101 = reserved ? 1110 = temperature sensor. ? 1111 = reserved. differential mode (noninverting inpu t and inverting input respectively): 0000 = ana0 and ana1 ? 0001 = ana2 and ana3 ? 0010 = ana4 and ana5 ? 0011 = ana1 and ana0 ? 0100 = ana3 and ana2 ? 0101 = ana5 and ana4 ? 0110 = ana6 and ana5 ? 0111 = ana0 and ana2 ? 1000 = ana0 and ana3 ? 1001 = ana0 and ana4 ? 1010 = ana0 and ana5 ? 1011 = reserved ? 1100 = reserved ? 1101 = reserved ? 1110 = reserved ? 1111 = manual offset calibration mode adc control/status register 1 the adc control/statu s register 1 (adcctl1) configures the input buffer stage, enables the threshold interrupts and contains the status of both threshold triggers. it is also used to select the voltage reference configuration.
ps022827-1212 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f082a series product specification 136 adc data high byte register the adc data high byte (adcd_h) register contains the upper eight bits of the adc output. the output is an 13-bit two?s compleme nt value. during a single-shot conversion, this value is invalid. access to the adc data hi gh byte register is read-only. reading the adc data high byte regi ster latches data in the adc low bits register. table 74. adc control/status register 1 (adcctl1) bit 7 6 5 4 3 2 1 0 field refselh reserved bufmode[2:0] reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f71h bit description [7] ? refselh voltage reference level select high bit in conjunction with the low bit (refsell) in adc control register 0, this determines the level of the internal voltage reference; the following details the effects of {refselh, refsell}; this reference is independent of the comparator reference. 00= internal reference disabled, reference comes from external pin. ? 01= internal refere nce set to 1.0 v. ? 10= internal reference set to 2.0 v (default). ? 11= reserved. [6:3] reserved these bits are reserved and must be programmed to 0000. [2:0] ? bufmode[2:0] input buffer mode select 000 = single-ended, unbuffered input. ? 001 = single-ended, buffered input with unity gain. ? 010 = reserved. ? 011 = reserved. ? 100 = differential, unbuffered input. ? 101 = differential, buffer ed input with unity gain. ? 110 = reserved. ? 111 = reserved.
ps022827-1212 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f082a series product specification 137 adc data low byte register the adc data low byte (adcd_l) register co ntains the lower bits of the adc output plus an overflow status bit. the output is a 13-bit two?s complement value. during a sin- gle-shot conversion, this valu e is invalid. access to the adc data low byte register is read-only. reading the adc data high byte register latches data in the adc low bits register. table 75. adc data high byte register (adcd_h) bit 7 6 5 4 3 2 1 0 field adcdh reset xxxxxxxx r/w rrrrrrrr address f72h x = undefined. bit description [7:0] ? adcdh adc data high byte this byte contains the upper eight bits of the adc output. these bits are not valid during a sin- gle-shot conversion. during a continuous conversion, the most recent conversion output is held in this register. these bits are undefined after a reset. table 76. adc data low byte register (adcd_l) bit 7 6 5 4 3 2 1 0 field adcdl reserved ovf reset xxxxxxxx r/w rrrrrrrr address f73h x = undefined. bit description [7:3] ? adcdl adc data low bits these bits are the least significant five bits of the 13-bits of the adc output. these bits are undefined after a reset.
ps022827-1212 p r e l i m i n a r y adc control register definitions z8 encore! xp ? f082a series product specification 138 [2:1] reserved these bits are reserved and must be undefined. [0] ? ovf overflow status 0 = a hardware overflow did not occur in the adc for the current sample. 1= a hardware overflow did occur in the adc for the current sample, therefore the current sample is invalid. bit description (continued)
ps022827-1212 p r e l i m i n a r y low power operational amplifier z8 encore! xp ? f082a series product specification 139 low power operational amplifier the lpo is a general-purpose low power operatio nal amplifier. each of the three ports of the amplifier is accessible from the package pi ns. the lpo contains only one pin configu- ration: ana0 is the output/feedback node, ana1 is the inverting input and ana2 is the noninverting input. operation to use the lpo, it must be enabled in the power control register 0 (pwrctl0) . the default state of the lpo is off. to use the lpo, the lpo bit must be cleared by turning it on (for details, see the power control register 0 section on page 33). when making normal adc measurements on ana0 (i.e., measurements no t involving the lpo output), the lpo bit must be turned off. turning the lpo bit on interferes with normal adc measurements. the lpo bit enables the amplifie r even in stop mode. if the amplifier is not required in stop mode, disable it. failing to perform th is results in stop mode currents higher than necessary. as with other adc measurements, any pins u sed for analog purposes must be configured as such in the gpio registers. see the port a?d alternate function subregisters section on page 47 for details. lpo output measurements are made on ana0, as selected by the anain[3:0] bits of adc control register 0. it is also possibl e to make single-ended measurements on ana1 and ana2 while the amplifier is enabled, whic h is often useful for determining offset con- ditions. differential measurements between ana0 and ana2 may be useful for noise cancellation purposes. if the lpo output is routed to the adc, then the buffmode [2:0] bits of adc control/sta- tus register 1 must also be configured fo r unity-gain buffered operation. sampling the lpo in an unbuffered mode is not recommended. when either input is overdriven, the amplifier output satura tes at the positive or negative supply voltage. no instability results. caution:
ps022827-1212 p r e l i m i n a r y comparator z8 encore! xp ? f082a series product specification 140 comparator the z8 encore! xp f082a series devices feat ure a general purpose comparator that com- pares two analog input signals. these analog signals may be external stimulus from a pin (cinp and/or cinn) or internally generated signals. both a progra mmable voltage refer- ence and the temperature sensor output voltage are available internally. the output is available as an interrupt source or can be routed to an external pin. operation when the positive comparator input exceeds th e negative input by more than the specified hysteresis, the output is a logic high. when the negative input ex ceeds the positive by more than the hysteresis, the output is a lo gic low. otherwise, the comparator output retains its present value. see table 141 on page 238 for details. the comparator may be powered down to reduce supply current. see the power control register 0 section on page 33 for details. because of the propagation delay of the co mparator, zilog does not recommend enabling or reconfiguring the comparat or without first disabling the interrupts and wa iting for the comparator output to settle. doing so can result in spurious interrupts. figure 20. comparator block diagram cinp pin temperature sensor inpsel innsel cinn pin comparator internal reference reflvl + - to cout pin to interrupt controller caution:
ps022827-1212 p r e l i m i n a r y comparator control register definition z8 encore! xp ? f082a series product specification 141 the following code example illustrates ho w to safely enable the comparator: di ld cmp0, r0 ; load some new configuration nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei comparator control register definition the comparator control register (cmp0) co nfigures the comparator inputs and sets the value of the internal voltage reference. table 77. comparator control register (cmp0) bit 7 6 5 4 3 2 1 0 field inpsel innsel reflvl reserved (20-/28-pin) reflvl (8-pin) reset 00010100 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f90h bit description [7] ? inpsel signal select for positive input 0 = gpio pin used as positive comparator input. 1 = temperature sensor used as positive comparator input. [6] ? innsel signal select for negative input 0 = internal reference disabled, gpio pin used as negative comparator input. 1 = internal reference enabled as negative comparator input.
ps022827-1212 p r e l i m i n a r y comparator control register definition z8 encore! xp ? f082a series product specification 142 [5:2] ? reflvl internal reference voltage level this reference is independent of the adc voltage reference. note: 8-pin devices contain two additional lsbs for increased resolution. for 20-/28-pin devices: 0000 = 0.0 v ? 0001 = 0.2 v ? 0010 = 0.4 v ? 0011 = 0.6 v ? 0100 = 0.8 v ? 0101 = 1.0 v (default) ? 0110 = 1.2 v ? 0111 = 1.4 v ? 1000 = 1.6 v ? 1001 = 1.8 v ? 1010?1111 = reserved bit description (continued)
ps022827-1212 p r e l i m i n a r y comparator control register definition z8 encore! xp ? f082a series product specification 143 [1:0] for 8-pin devices, the following voltages can be configured; for 20- and 28-pin devices, these bits are reserved. 000000 = 0.00 v ? 000001 = 0.05 v ? 000010 = 0.10 v ? 000011 = 0.15 v ? 000100 = 0.20 v ? 000101 = 0.25 v ? 000110 = 0.30 v ? 000111 = 0.35 v ? 001000 = 0.40 v ? 001001 = 0.45 v ? 001010 = 0.50 v ? 001011 = 0.55 v ? 001100 = 0.60 v ? 001101 = 0.65 v ? 001110 = 0.70 v ? 001111 = 0.75 v ? 010000 = 0.80 v ? 010001 = 0.85 v ? 010010 = 0.90 v ? 010011 = 0.95 v ? 010100 = 1.00 v (default) ? 010101 = 1.05 v ? 010110 = 1.10 v ? 010111 = 1.15 v ? 011000 = 1.20 v ? 011001 = 1.25 v ? 011010 = 1.30 v ? 011011 = 1.35 v ? 011100 = 1.40 v ? 011101 = 1.45 v ? 011110 = 1.50 v ? 011111 = 1.55 v ? 100000 = 1.60 v ? 100001 = 1.65 v ? 100010 = 1.70 v ? 100011 = 1.75 v ? 100100 = 1.80 v bit description (continued)
ps022827-1212 p r e l i m i n a r y temperature sensor z8 encore! xp ? f082a series product specification 144 temperature sensor the on-chip temperature sensor allows you to measure temperature on the die with either the on-board adc or on-board comparator. this block is factory calibrated for in-circuit software correction. uncalibrated accuracy is significantly worse, therefore the tempera- ture sensor is not recomm ended for uncalibrated use. temperature sensor operation the on-chip temperature sensor is a proportio nal to absolute temperature (ptat) topol- ogy. a pair of flash option bytes contain th e calibration data. the temperature sensor can be disabled by a bit in the power control register 0 section on page 33 to reduce power consumption. the temperature sensor can be directly read by the adc to determine the absolute value of its output. the temperature sensor output is also available as an input to the comparator for threshold type measurement dete rmination. the accuracy of th e sensor when used with the comparator is substantially less than when measured by the adc. if the temperature sensor is routed to the adc , the adc must be configured in unity-gain buffered mode (for details, see the input buffer stage section on page 133). the value read back from the adc is a signed numb er, although it is always positive. the sensor is factory-trimmed through the adc using the external 2.0 v reference. unless the sensor is retrimmed for use with a differen t reference, it is most accurate when used with the external 2.0 v reference. because this sensor is an on-chip sensor, z ilog recommends that th e user account for the difference between ambient and die temperat ure when inferring ambient temperature con- ditions. during normal operation, the die undergoes heating that causes a mismatch between the ambient temperature and that m easured by the sensor. for best results, the z8 encore! xp device must be placed into stop mode for su fficient time such that the die and ambient temperatures converge (this tim e is dependent on the thermal design of the system). the temperature sensor measurement must then be made immediately after recovery from stop mode. the following equation defines the transfer function between the temperature sensor out- put voltage and the die temperature. this is needed for comparator threshold measure- ments. v 0.01 t 0.65 + ? =
ps022827-1212 p r e l i m i n a r y temperature sensor operation z8 encore! xp ? f082a series product specification 145 in the above equation, t is the temperature in c; v is the sensor output in volts. assuming a compensated adc measurement, th e following equation defines the relation- ship between the adc reading and the die temperature: in the above equation, t is the temperatur e in c; adc is the 10-bit compensated adc value; and tscal is the temperature sensor ca libration value, ignori ng the two least sig- nificant bits of the 12-bit value. see the temperature sensor calibration data section on page 171 for the location of tscal. calibration the temperature sensor undergoes calibration during the manufacturing process and is maximally accurate at 30c. accuracy decreases as measured temperatures move further from the calibration point. t25128 ? ?? adc tscal 11:2 ?? ? ?? ? 30 + =
ps022827-1212 p r e l i m i n a r y flash memory z8 encore! xp ? f082a series product specification 146 flash memory the products in the z8 encore! xp f082a series featur e a nonvolatile flash memory of 8 kb (8192), 4 kb (4096), 2 kb (2048 bytes), or 1 kb (1024) with read/write/erase capa- bility. the flash memory can be programmed and erased in-circuit by user code or through the on-chip debugger. the features include: ? user controlled read and write protect capability ? sector-based write protection scheme ? additional protection schemes agains t accidental program and erasure architecture the flash memory array is a rranged in pages with 512 bytes per page. the 512-byte page is the minimum flash block size that can be era sed. each page is divided into 8 rows of 64 bytes. for program or data protection, the flash memory is also divided into sectors. in the z8 encore! xp f082a series, these sectors are either 1024 bytes (in the 8 kb devices) or 512 bytes (all other memory sizes) in size. page and sector sizes are not generally equal. the first 2 bytes of flash program memory are used as flash option bits. for more infor- mation about their operation, see the flash option bits chapter on page 159. table 78 describes the flash memory configuration for each device in the z8 encore! xp f082a series. figure 21 displays the flash memory arrangement. table 78. z8 encore! xp f082a series flash memory configurations part number flash size kb (bytes) flash pages program memory addresses flash sector size (bytes) z8f08xa 8 (8192) 16 0000h?1fffh 1024 z8f04xa 4 (4096) 8 0000h?0fffh 512 z8f02xa 2 (2048) 4 0000h?07ffh 512 z8f01xa 1 (1024) 2 0000h?03ffh 512
ps022827-1212 p r e l i m i n a r y flash information area z8 encore! xp ? f082a series product specification 147 flash information area the flash information area is separate from program memory and is mapped to the address range fe00h to ffffh . this area is readable but can not be erased or overwritten. factory trim values for the anal og peripherals are stored here. factory calibration data for the adc is also stored here. operation the flash controller programs and erases fl ash memory. the flash controller provides the proper flash controls and timing for byte programming, page erase and mass erase of flash memory. the flash controller contains several protection mechanisms to prevent accidental program- ming or erasure. these mechanism operate on the page, sector and full-memory levels. figure 21. flash memory arrangement 4kb flash program memory 0000 01ff 0200 0fff addresses (hex) 03ff 0400 05ff 0600 07ff 0800 09ff 0a00 0bff 0c00 0dff 0e00 2kb flash program memory 0000 addresses (hex) 07ff 05ff 0600 03ff 0400 01ff 0200 1kb flash program memory 0000 addresses (hex) 03ff 01ff 0200 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 sector 0 sector 1 sector 0 sector 1 sector 2 sector 3 8kb flash program memory 0000 03ff 0400 1fff addresses (hex) 07ff 0800 0bff 0c00 0fff 1000 13ff 1400 17ff 1800 1bff 1c00 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 148 figure 22 displays a basic flash controlle r flow. the following subsections provide details about the various operations displayed in figure 22. figure 22. flash controller operation flow chart reset page 73h no yes 8ch no yes program/erase enabled 95h no yes write fctl lock state 0 lock state 1 write fctl write fctl byte program page erase write page select register write page select register page in no no unlocked protected sector? writes to page select register in lock state 1 result in a return to lock state 0 page select yes values match? yes
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 149 flash operation timing using the flash freq uency registers before performing either a program or erase operation on flash memory, you must first configure the flash frequency high and low byte registers. the flash frequency regis- ters allow programming and erasing of the fl ash with system clock frequencies ranging from 32 khz (32768 hz) through 20 mhz. the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control timing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system cl ock frequency (in khz). this value is calcu- lated using the following equation: flash programming and erasure are not supp orted for system clock frequencies below 32 khz (32768 hz) or above 20 mhz. the flash frequency high and low byte registers must be loaded with the correct value to en sure operation of the z8 encore! xp f082a series devices. flash code protection against external access the user code contained within the flash memory can be protected against external access by the on-chip debugger. programming the fr p flash option bit prevents reading of the user code with the on-chip debugger. see the flash option bits chapter on page 159 and the on-chip debugger chapter on page 180 for more information. flash code protection agai nst accidental program and erasure the z8 encore! xp f082a series provides sever al levels of protection against accidental program and erasure of the flash memory contents. this protection is provided by a com- bination of the flash option bits, the register locking mechanism, the page select redun- dancy and the sector level protectio n control of the flash controller. flash code protection us ing the flash option bits the frp and fwp flash option bits combine to provide three levels of flash program memory protection, as shown in table 79. see the flash option bits chapter on page 159 for more information. ffreq[15:0] system clock frequency (hz) 1000 ----------------------------------------------------- ------------ - = caution:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 150 . flash code protection us ing the flash controller at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory, first write the page select register with the target page. unlock the flash controlle r by making two consecutive writes to the flash control register with the values 73h and 8ch , sequentially. the page select regis- ter must be rewritten with the target page. if the two page select writes do not match, the controller reverts to a locked state. if the two writes match, the selected page becomes active. see figure 22 on page 148 for details. after unlocking a specific page, you can enable either page program or erase. writing the value 95h causes a page erase only if the active page resides in a sector that is not pro- tected. any other value written to the flash co ntrol register locks the flash controller. mass erase is not allowed in the user co de but only in thro ugh the debug port. after unlocking a specific page, you can also wr ite to any byte on that page. after a byte is written, the page remains unlocked, allowing for subsequent writes to other bytes on the same page. further writes to the flash control register cause the active page to revert to a locked state. sector-based flash protection the final protection mechanism is implemente d on a per-sector basis. the flash memories of z8 encore! xp devices are divided into ma ximum number of 8 sectors. a sector is 1/8 of the total flash memory size unless this valu e is smaller than the page size ? in which case, the sector and page sizes are equal. on z8 encore! f082a series devices, the sector size is varied according to the fl ash memory configuration shown in table 78 on page 146. the flash sector protect register can be co nfigured to prevent sectors from being pro- grammed or erased. after a sector is protected, it cannot be unprotected by user code. the flash sector protect register is cleared af ter reset, and any previously-written protection values are lost. user code must write this regi ster in their initialization routine if they pre- fer to enable sector protection. the flash sector protect register shares its register file address with the page select register. the flash sector protect register is accessed by writing the flash control regis- table 79. flash code protection using the flash option bits fwp flash code protection description 0 programming and erasing disabled for all of flash program mem- ory. in user code programming, page erase and mass erase are all disabled. mass erase is available through the on-chip debugger. 1 programming, page erase and mass erase are enabled for all of flash program memory.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 151 ter with 5eh . after the flash sector protect register is selected, it can be accessed at the page select register address. when user code writes the flash sector protect register, bits can only be set to 1. thus, sectors can be protected, but not unprotected, via register write operations. writing a value other than 5eh to the flash control register deselects the flash sector protect register and reen ables access to the page select register. observe the following procedure to setup th e flash sector protect register from user code: 1. write 00h to the flash control register to reset the flash controller. 2. write 5eh to the flash control register to select the flash sector protect register. 3. read and/or write the flash sector protect register which is now at register file address ff9h . 4. write 00h to the flash control register to return the flash controller to its reset state. ? the sector protect register is initialized to 0 on reset, putting each sector into an unpro- tected state. when a bit in the sector protec t register is written to 1, the corresponding sector is no longer written or erased by the cpu. external flash programming through the ocd or via the flash controller bypass mode ar e unaffected. after a bit of the sector pro- tect register has been set, it cannot be cleared except by powering down the device. byte programming flash memory is enabled for byte programming after unlocking the flash controller and successfully enabling either mass erase or page erase. when the flash controller is unlocked and mass erase is successfully co mpleted, all program memory locations are available for byte programming. in contrast , when the flash controller is unlocked and page erase is successfully completed, only the locations of the selected page are available for byte programming. an erased flash byte contains all 1?s ( ffh ). the programming operation can only be used to change bits from 1 to 0. to change a flash bit (or multiple bits) from 0 to 1 requires execution of eith er the page erase or mass erase commands. byte programming can be accomplished using the on-chip debugger?s write memory command or ez8 cpu execution of the ldc or ldci instructions. refer to the ez8 cpu core user manual (um0128) , available for download on www.zilog.com , for a descrip- tion of the ldc and ldci inst ructions. while the flash co ntroller programs the flash memory, the ez8 cpu idles but the system clock and on-chip peripherals continue to oper- ate. to exit programming mode and lock the flash, write any value to the flash control register, except the mass erase or page erase commands.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 152 the byte at each address of the flash memo ry cannot be programm ed (any bits written to 0) more than twice before an erase cycle occurs. doing so may r esult in corrupted data at the target byte. page erase the flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the flash page select register identi- fies the page to be erased. only a page resi ding in an unprotected sector can be erased. with the flash controller unlocked and the active page set, writing the value 95h to the flash control register initiates the page erase operation. while the flash controller exe- cutes the page erase operation, the ez8 cp u idles but the system clock and on-chip peripherals continue to operate. the ez8 cpu resumes operation after the page erase operation completes. if the page erase operation is performed using the on-chip debug- ger, poll the flash status register to determ ine when the page erase operation is complete. when the page erase is complete, the flash controller returns to its locked state. mass erase the flash memory can also be mass erased us ing the flash controller, but only by using the on-chip debugger. mass erasing the flas h memory sets all bytes to the value ffh . with the flash controller unlocked and the mass erase successfully enabled, writing the value 63h to the flash control register initiate s the mass erase operation. while the flash controller executes the mass erase oper ation, the ez8 cpu idles but the system clock and on-chip peripherals continue to operate. using the on-chip debugger, poll the flash status register to determine when th e mass erase operation is complete. when the mass erase is complete, the flash cont roller returns to its locked state. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster row program- ming algorithms by controlling the flash programming signals directly. row programming is recommended for gang pr ogramming applications and large volume customers who do not require in-circuit initia l programming of the flash memory. page erase operations are also supported wh en the flash controller is bypassed. for more information about bypassing the flash controller, refer to the third-party flash programming support for z8 encore! mcus application note (an0117) , which is avail- able for download on www.zilog.com . caution:
ps022827-1212 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f082a series product specification 153 flash controller behavior in debug mode the following changes in behavior of the fl ash controller occur when the flash control- ler is accessed using the on-chip debugger: ? the flash write protect option bit is ignored. ? the flash sector protect register is ignored for programming and erase operations. ? programming operations are not limited to the page selected in the page select register. ? bits in the flash sector protect register can be written to one or zero. ? the second write of the page select regist er to unlock the flash controller is not necessary. ? the page select register can be written when the flash controller is unlocked. ? the mass erase command is enabled th rough the flash control register. for security reasons, the flash controller allows only a single page to be opened for write/ erase. when writing multiple flash pages, the flash controller must go through the unlock sequence again to select another page. flash control register definitions this section defines the features of the following flash control registers. flash control register : see page 153 flash status register : see page 155 flash page select register : see page 156 flash sector protect register : see page 157 flash frequency high and low byte registers : see page 157 flash control register the flash controller must be unlocked usin g the flash control (fctl) register before programming or erasing the fl ash memory. writing the sequence 73h 8ch , sequentially, to the flash control register unlocks the fl ash controller. when the flash controller is unlocked, the flash memory ca n be enabled for mass erase or page erase by writing the appropriate enable command to the fctl. pa ge erase applies only to the active page selected in flash page select register. mass erase is enabled only through the on-chip caution:
ps022827-1212 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f082a series product specification 154 debugger. writing an invalid va lue or an invalid sequence returns the flash controller to its locked state. the write-only flash contro l register shares its register file address with the read-only flash status register.
ps022827-1212 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f082a series product specification 155 flash status register the flash status (fstat) register indicates th e current state of the flash controller. this register can be read at any time. the read-o nly flash status register shares its register file address with the write-o nly flash control register. table 80. flash control register (fctl) bit 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww address ff8h bit description [7:0] ? fcmd flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command (must be third command in sequence to initiate page erase). 63h = mass erase command (must be third command in sequence to initiate mass erase). 5eh = enable flash sector protect register access table 81. flash status register (fstat) bit 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr address ff8h bit description [7:6] these bits are reserved and must be programmed to 00. [5:0] ? fstat flash controller status 000000 = flash controller locked. ? 000001 = first unlock command received (73h written). ? 000010 = second unlock command received (8ch written). ? 000011 = flash controller unlocked. 000100 = sector protect register selected. 001xxx = program operation in progress. 010xxx = page erase operation in progress. 100xxx = mass erase operation in progress.
ps022827-1212 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f082a series product specification 156 flash page select register the flash page select (fps) register shares address space with the flash sector protect register. unless the flash controller is unlo cked and written with 5eh, writes to this address target the flash page select register. the register is used to select one of the available flash memory pages to be programmed or erased. each flash page contains 512 bytes of flash memory. during a page erase operation, all flash memory having addresses with the most significant 7 bits given by fps[6:0] are chosen fo r program/erase operation. table 82. flash page select register (fps) bit 7 6 5 4 3 2 1 0 field info_en page reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff9h bit description [7] ? info_en information area enable 0 = information area us not selected. 1 = information area is selected. the information area is mapped into the program memory address space at addresses fe00h through ffffh . [6:0] ? page page select this 7-bit field identifies the flash memory pa ge for page erase and page unlocking. program memory address[15:9] = page[6:0]. for the z8 f08xx devices, the upper 3 bits must be zero. for the z8f04xx devices, the up per 4 bits must be zero. for z8f02xx devices, the upper 5 bits must always be 0. for the z8f01xx device s, the upper 6 bits must always be 0.
ps022827-1212 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f082a series product specification 157 flash sector protect register the flash sector protect (fprot) register is shared with the flash page select register. when the flash control register is written with 5eh , the next write to this address targets the flash sector protect register. in all othe r cases, it targets the flash page select regis- ter. this register selects one of the 8 available flash memory sectors to be protected. the reset state of each sector protect bit is an unprotected state. after a sector is protected by setting its corresponding register bit, it cannot be un protected (the register bit cannot be cleared) without powering down the device. flash frequency high and low byte registers the flash frequency high (ffreqh) and lo w byte (ffreql) registers combine to form a 16-bit value, ffreq, to control tim ing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz) and is calculated us ing the following equation: table 83. flash sector protect register (fprot) bit 7 6 5 4 3 2 1 0 field sprot7 sprot6 sprot5 sprot4 sprot3 sprot2 sprot1 sprot0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff9h bit description [7:0] ? sprot n sector protection each bit corresponds to a 1024-byte flash sector on devices in the 8k range, while the remaining devices correspond to a 512-byte flash sector. to determine the appropriate flash memory sector address range and sector number for your z8f082a series product, please refer to table 78 on page 146 and to figure 21, which follows the table. ? for z8f08xa and z8f04xa devices, all bits are used. ? for z8f02xa devices, the upper 4 bits are unused. ? for z8f01xa devices, the upper 6 bits are unused. ffreq[15:0] ffreqh[ 7:0],ffreql[7:0] ?? system clock frequency 1000 --------------------------------------- ---------------- ==
ps022827-1212 p r e l i m i n a r y flash control register definitions z8 encore! xp ? f082a series product specification 158 the flash frequency high and low byte regist ers must be loaded with the correct value to ensure proper operation of the device. al so, flash programming and erasure is not sup- ported for system clock frequencies below 20 khz or above 20 mhz. table 84. flash frequency high byte register (ffreqh) bit 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ffah bit description [7:0] ? ffreqh flash frequency high byte high byte of the 16-bit flash frequency value. table 85. flash frequency low byte register (ffreql) bit 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w address ffbh bit description [7:0] ? ffreql flash frequency low byte low byte of the 16-bit flash frequency value. caution:
ps022827-1212 p r e l i m i n a r y flash option bits z8 encore! xp ? f082a series product specification 159 flash option bits programmable flash option bits allow user co nfiguration of certain aspects of z8 encore! xp f082a series operation. the feature configuration data is stored in flash program memory and loaded into holding registers du ring reset. the features available for control through the flash option bits include: ? watchdog timer time-out response selection?interrupt or system reset ? watchdog timer always on (enabled at reset) ? the ability to prevent unwa nted read access to user code in program memory ? the ability to prevent accidental programming and erasure of all or a portion of the user code in program memory ? voltage brown-out configuration-always en abled or disabled during stop mode to reduce stop mode power consumption ? oscillator mode selection-for high, medium and low power crystal oscillators, or exter- nal rc oscillator ? factory trimming information for the intern al precision oscillator and low voltage de- tection ? factory calibration values for adc, temperature sensor and watchdog timer compen- sation ? factory serialization and random ized lot identifier (optional) operation this section describes the type and configur ation of the programmable flash option bits. option bit configuration by reset each time the flash option bits are programm ed or erased, the device must be reset for the change to take effect. during any reset operation (system reset, power-on reset, or stop mode recovery), the flash option bits are automatically read from flash program memory and written to the option configuratio n registers. the option configuration reg- isters control the operation of the devices w ithin the z8 encore! xp f082a series. option bit control is established before the device exits reset and the ez8 cpu begins code exe- cution. the option configuration registers are not part of the register file and are not accessible for read or write access.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 160 option bit types this section describes the five types of flash option bits. user option bits the user option bits are contained in the first two bytes of program memory. user access to these bits has been provided because these locations contain application-specific device configurations. the information contained here is lost when page 0 of the program mem- ory is erased. trim option bits the trim option bits are contained in the info rmation page of the flash memory. these bits are factory programmed values required to optimize the operation of onboard analog cir- cuitry and cannot be permanen tly altered. program memory may be erased without endan- gering these values. it is possible to alter working values of these bits by accessing the trim bit address and data registers, but these working values are lost after a power loss or any other reset event. there are 32 bytes of trim data. to modify on e of these values the user code must first write a value between 00h and 1fh into the trim bit address register. the next write to the trim bit data register changes the working value of the target trim data byte. reading the trim data requires the u ser code to write a value between 00h and 1fh into the trim bit address register. the next read fro m the trim bit data register returns the working value of the target trim data byte. the trim address range is from information address 20?3f only. the remainder of the information page is not accessible through the trim bit address and data registers. calibration option bits the calibration option bits are also contained in the information page. these bits are fac- tory-programmed values intended for use in so ftware correcting the device?s analog per- formance. to read these values, the user code must employ the ldc instruction to access the information area of the address space as defined in see the flash information area sec- tion on page 17. serialization bits as an optional feature, zilog is able to provide factory-pr ogrammed serialization. for seri- alized products, the individual devices are pr ogrammed with unique serial numbers. these serial numbers are binary values, four bytes in length. the numbers increase in size with each device, but gaps in th e serial sequence may exist. note:
ps022827-1212 p r e l i m i n a r y flash option bit control register z8 encore! xp ? f082a series product specification 161 these serial numbers are stored in the flash information page and are unaffected by mass erasure of the device's flash memory. see th e reading the flash information page section below and the serialization data section on page 173 for more details. randomized lot identification bits as an optional feature, zilog is able to pr ovide a factory-programm ed random lot identi- fier. with this feature, all devices in a give n production lot are programmed with the same random number. this random number is uniquely regenerated for each successive produc- tion lot and is not like ly to be repeated. the randomized lot identifier is a 32 byte bi nary value, stored in the flash information page and is unaffected by mass erasure of the device?s flash memory. see reading the flash information page, below, and the randomized lot identifier section on page 174 for more details. reading the flash information page the following code example shows how to r ead data from the flash information area. ; get value at info address 60 (fe60h) ldx fps, #%80 ; enable access to flash info page ld r0, #%fe ld r1, #%60 ldc r2, @rr0 ; r2 now contains the calibration value flash option bit control register definitions this section briefly describes the features of the trim bit address and data registers. trim bit address register the trim bit address (trmadr) register contai ns the target address for an access to the trim option bits (table 86). table 86. trim bit address register (trmadr) bit 7 6 5 4 3 2 1 0 field trmadr: trim bit address (00h to 1fh) reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff6h
ps022827-1212 p r e l i m i n a r y flash option bit address space z8 encore! xp ? f082a series product specification 162 trim bit data register the trim bid data (trmdr) register contains the read or write data for access to the trim option bits (table 87). flash option bit address space the first two bytes of flash program memory at addresses 0000h and 0001h are reserved for the user-programmable flash option bits. flash program memo ry address 0000h table 87. trim bit data register (trmdr) bit 7 6 5 4 3 2 1 0 field trmdr: trim bit data reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address ff7h table 88. flash option bits at program memory address 0000h bit 7 6 5 4 3 2 1 0 field wdt_res wdt_ao osc_sel[1:0] vbo_ao frp reserved fwp reset u uuuuuuu r/w r/w r/w r/w r/w r/w r/w r/w r/w address program memory 0000h note: u = unchanged by reset. r/w = read/write. bit description [7] ? wdt_res watchdog timer reset 0 = watchdog timer time-out generates an inte rrupt request. in terrupts must be globally enabled for the ez8 cpu to acknowledge the interrupt request. 1 = watchdog timer time-out causes a system re set. this setting is the default for unpro- grammed (erased) flash. [6] ? wdt_ao watchdog timer always on 0 = watchdog timer is automatically enabled upon application of system power. watch- dog timer can not be disabled. 1 = watchdog timer is enabled upon executio n of the wdt instruction. once enabled, the watchdog timer can only be disabled by a reset or stop mode recovery. this setting is the default for unprogrammed (erased) flash.
ps022827-1212 p r e l i m i n a r y flash option bit address space z8 encore! xp ? f082a series product specification 163 [5:4] ? osc_sel[1:0] oscillator mode selection 00 = on-chip oscillator configured for us e with external rc networks (<4 mhz). 01 = minimum power for use with very low frequency crystals (32 khz to 1.0 mhz). 10 = medium power for use with medium frequency crystals or ceramic resonators (0.5 mhz to 5.0 mhz). 11 = maximum power for use with high freque ncy crystals (5.0 mhz to 20.0 mhz). this setting is the default for unprogrammed (erased) flash. [3] ? vbo_ao voltage brown-out protection always on 0 = voltage brown-out protection can be dis abled in stop mode to reduce total power consumption. for the block to be disabled, the power control register bit must also be written (see the power control register definitions section on page 33). 1 = voltage brown-out protection is always enabled including during stop mode. this setting is the default for unprogrammed (erased) flash. [2] ? frp flash read protect 0 = user program code is inaccessible. limited control features are available through the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this setting is the default for unprogrammed (erased) flash. [1] reserved this bit is reserved and must be programmed to 1. [0] ? fwp flash write protect this option bit provides fl ash program memory protection: 0 = programming and erasure disabled for all of flash program memory. programming, page erase and mass erase through user code is disabled. mass erase is available using the on-chip debugger. 1 = programming, page erase and mass erase are enabled for all of flash program memory. bit description (continued)
ps022827-1212 p r e l i m i n a r y flash option bit address space z8 encore! xp ? f082a series product specification 164 flash program memo ry address 0001h table 89. flash options bits at program memory address 0001h bit 7 6 5 4 3 2 1 0 field reserved xtldis reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address program memory 0001h note: u = unchanged by reset. r/w = read/write. bit description [7:5] reserved these bits are reserved and must be programmed to 111. [4] ? xtldis state of the crystal oscillator at reset this bit only enables the crystal oscillator. its selection as a system clock must be performed manually. 0 = crystal oscillator is enabled during reset, resulting in longer reset timing. 1 = crystal oscillator is disabled during reset, resulting in shorter reset timing. ? caution: programming the xtldis bit to zero on 8-pin versions of this device prevents any further communication via the debug pin due to the fact that the xin and dbg functions are shared on pin 2 of this package. do not progra m this bit to zero on 8-pin devices unless further debugging or flash programming is not required. [3:0] reserved these bits are reserved and must be programmed to 1111.
ps022827-1212 p r e l i m i n a r y trim bit address space z8 encore! xp ? f082a series product specification 165 trim bit address space all available trim bit addresses and their functions are listed in table 90 through table 95. trim bit address 0000h trim bit address 0001h table 90. trim options bits at address 0000h bit 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0020h note: u = unchanged by reset. r/w = read/write. bit description [7:0] reserved these bits are reserved; altering this regist er may result in incorrect device operation. table 91. trim option bits at 0001h bit 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0021h note: u = unchanged by reset. r/w = read/write. bit description [7:0] reserved these bits are reserved; altering this regist er may result in incorrect device operation.
ps022827-1212 p r e l i m i n a r y trim bit address space z8 encore! xp ? f082a series product specification 166 trim bit address 0002h trim bit address 0003h the lvd is available on 8-pin devices only. table 92. trim option bits at 0002h (tipo) bit 7 6 5 4 3 2 1 0 field ipo_trim reset u r/w r/w address information page memory 0022h note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? ipo_trim internal precision oscillator trim byte contains trimming bits for th e internal precision oscillator. table 93. trim option bits at address 0003h (tlvd) bit 7 6 5 4 3 2 1 0 field reserved lvd_trim reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0023h note: u = unchanged by reset. r/w = read/write. bit description [7:5] reserved these bits are reserved and must be programmed to 111. [4:0] ? lvd_trim low voltage detect trim m this trimming affects the low vo ltage detection threshold. each lsb represents a 50 mv change in the threshold level. alternatively, th e low voltage threshold may be computed from the options bit value by the following equation: these values are tabulated in table 94. note: lvd_lvl 3.6 v lvd_trim 0.05 v ? ? =
ps022827-1212 p r e l i m i n a r y trim bit address space z8 encore! xp ? f082a series product specification 167 table 94. lvd trim values lvd_trim lvd threshold (v) typical description 00000 3.60 maximum lvd threshold 00001 3.55 00010 3.50 00011 3.45 00100 3.40 00101 3.35 00110 3.30 00111 3.25 01000 3.20 01001 3.15 01010 3.10 default on reset 01011 3.05 01100 3.00 01101 2.95 01110 2.90 01111 2.85 10000 2.80 10001 2.75 10010 2.70 10011 to 11111 2.70 to 1.65 minimum lvd threshold
ps022827-1212 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f082a series product specification 168 trim bit address 0004h zilog calibration data this section briefly describes the features of the following flash op tion bit calibration reg- isters. adc calibration data : see page 169 temperature sensor calibration data : see page 171 watchdog timer calibration data : see page 172 serialization data : see page 173 randomized lot identifier : see page 174 table 95. trim option bits at 0004h bit 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0024h note: u = unchanged by reset. r/w = read/write. bit description [7:0] reserved these bits are reserved; altering this regist er may result in incorrect device operation.
ps022827-1212 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f082a series product specification 169 adc calibration data table 96. adc calibration bits bit 7 6 5 4 3 2 1 0 field adc_cal reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 0060h?007dh note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? adc_cal analog-to-digital converter calibration values contains factory-calibrated values for adc gain and offset compensation. each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration. these values are read by the software to compensate adc measurements as described in the software compensation procedure using factory calibration data section on page 129. the location of each calibration byte is provided in table 97. table 97. adc calibration data location info page address memory address compensation usage adc mode reference type 60 fe60 offset single-ended unbuffered internal 2.0 v 08 fe08 gain high byte single-ended unbuffered internal 2.0 v 09 fe09 gain low byte single-ended unbuffered internal 2.0 v 63 fe63 offset single-ended unbuffered internal 1.0 v 0a fe0a gain high byte single-ended unbuffered internal 1.0 v 0b fe0b gain low byte single-ended unbuffered internal 1.0 v 66 fe66 offset single-ended unbuffered external 2.0 v 0c fe0c gain high byte single-ended unbuffered external 2.0 v 0d fe0d gain low byte single-ended unbuffered external 2.0 v 69 fe69 offset single-ended 1x buffered internal 2.0 v 0e fe0e gain high byte single-ended 1x buffered internal 2.0 v 0f fe0f gain low byte single-ended 1x buffered internal 2.0 v 6c fe6c offset single-ended 1x buffered external 2.0 v 10 fe10 gain high byte single-ended 1x buffered external 2.0 v 11 fe11 gain low byte single-ended 1x buffered external 2.0 v 6f fe6f offset differential unbuffered internal 2.0 v
ps022827-1212 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f082a series product specification 170 12 fe12 positive gain high byte differential unbuffered internal 2.0 v 13 fe13 positive gain low byte differential unbuffered internal 2.0 v 30 fe30 negative gain high byte differential unbuffered internal 2.0 v 31 fe31 negative gain low byte differential unbuffered internal 2.0 v 72 fe72 offset differential unbuffered internal 1.0 v 14 fe14 positive gain high byte differential unbuffered internal 1.0 v 15 fe15 positive gain low byte differential unbuffered internal 1.0 v 32 fe32 negative gain high byte differential unbuffered internal 1.0 v 33 fe33 negative gain low byte differential unbuffered internal 1.0 v 75 fe75 offset differential unbuffered external 2.0 v 16 fe16 positive gain high byte differential unbuffered external 2.0 v 17 fe17 positive gain low byte differential unbuffered external 2.0 v 34 fe34 negative gain high byte differential unbuffered external 2.0 v 35 fe35 negative gain low byte differential unbuffered external 2.0 v 78 fe78 offset differential 1x buffered internal 2.0 v 18 fe18 positive gain high byte differential 1x buffered internal 2.0 v 19 fe19 positive gain low byte differential 1x buffered internal 2.0 v 36 fe36 negative gain high byte differential 1x buffered internal 2.0 v 37 fe37 negative gain low byte differential 1x buffered internal 2.0 v 7b fe7b offset differential 1x buffered external 2.0 v 1a fe1a positive gain high byte differential 1x buffered external 2.0 v 1b fe1b positive gain low byte differential 1x buffered external 2.0 v 38 fe38 negative gain high byte differential 1x buffered external 2.0 v 39 fe39 negative gain low byte differential 1x buffered external 2.0 v table 97. adc calibration data location (continued) info page address memory address compensation usage adc mode reference type
ps022827-1212 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f082a series product specification 171 temperature sensor calibration data table 98. temperature sensor calibration high byte at 003a (tscalh) bit 7 6 5 4 3 2 1 0 field tscalh reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 003a note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? tscalh temperature sensor calibration high byte the tscalh and tscall bytes combine to form the 12-bit temperature sensor offset calibra- tion value. for more details, see temperature sensor operation on page 139. table 99. temperature sensor calibration low byte at 003b (tscall) bit 7 6 5 4 3 2 1 0 field tscall reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 003b note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? tscall temperature sensor calibration low byte the tscalh and tscall bytes combine to form the 12-bit temperature sensor offset calibra- tion value. for usage details, see the temperature sensor operation section on page 144.
ps022827-1212 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f082a series product specification 172 watchdog timer calibration data table 100. watchdog calibration high byte at 007eh (wdtcalh) bit 7 6 5 4 3 2 1 0 field wdtcalh reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 007eh note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? wdtcalh watchdog timer calibration high byte the wdtcalh and wdtcall bytes, when loaded into the watchdog timer reload regis- ters result in a one second time-out at room temperature and 3.3 v supply voltage. to use the watchdog timer calibration, user code must load wdtu with 0x00 , wdth with wdt- calh and wdtl with wdtcall.
ps022827-1212 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f082a series product specification 173 serialization data table 101. watchdog calibration low byte at 007fh (wdtcall) bit 7 6 5 4 3 2 1 0 field wdtcall reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 007fh note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? wdtcall watchdog timer calibration low byte the wdtcalh and wdtcall bytes, when loaded into the watchdog timer reload regis- ters result in a one second time-out at room temperature and 3.3 v supply voltage. to use the watchdog timer calibration, user code must load wdtu with 0x00, wdth with wdt- calh and wdtl with wdtcall. table 102. serial number at 001c - 001f (s_num) bit 7 6 5 4 3 2 1 0 field s_num reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address information page memory 001c-001f note: u = unchanged by reset. r/w = read/write. bit description [7:0] ? s_num serial number byte the serial number is a unique four-byte binary value. see table 103. table 103. serialization data locations info page address memory address usage 1c fe1c serial number byte 3 (most significant). 1d fe1d serial number byte 2. 1e fe1e serial number byte 1. 1f fe1f serial number byte 0 (least significant).
ps022827-1212 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f082a series product specification 174 randomized lot identifier table 104. lot id entification number (rand_lot) bit 7 6 5 4 3 2 1 0 field rand_lot reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w address interspersed throughout information page memory note: u = unchanged by reset. r/w = read/write. bit description [7] ? rand_lot randomized lot id the randomized lot id is a 32-byte binary value that changes for each production lot. see table 105. table 105. randomized lot id locations info page address memory address usage 3c fe3c randomized lot id byte 31 (most significant). 3d fe3d randomized lot id byte 30. 3e fe3e randomized lot id byte 29. 3f fe3f randomized lot id byte 28. 58 fe58 randomized lot id byte 27. 59 fe59 randomized lot id byte 26. 5a fe5a randomized lot id byte 25. 5b fe5b randomized lot id byte 24. 5c fe5c randomized lot id byte 23. 5d fe5d randomized lot id byte 22. 5e fe5e randomized lot id byte 21. 5f fe5f randomized lot id byte 20. 61 fe61 randomized lot id byte 19. 62 fe62 randomized lot id byte 18. 64 fe64 randomized lot id byte 17. 65 fe65 randomized lot id byte 16. 67 fe67 randomized lot id byte 15. 68 fe68 randomized lot id byte 14.
ps022827-1212 p r e l i m i n a r y zilog calibration data z8 encore! xp ? f082a series product specification 175 6a fe6a randomized lot id byte 13. 6b fe6b randomized lot id byte 12. 6d fe6d randomized lot id byte 11. 6e fe6e randomized lot id byte 10. 70 fe70 randomized lot id byte 9. 71 fe71 randomized lot id byte 8. 73 fe73 randomized lot id byte 7. 74 fe74 randomized lot id byte 6. 76 fe76 randomized lot id byte 5. 77 fe77 randomized lot id byte 4. 79 fe79 randomized lot id byte 3. 7a fe7a randomized lot id byte 2. 7c fe7c randomized lot id byte 1. 7d fe7d randomized lot id byte 0 (least significant). table 105. randomized lot id locations (continued) info page address memory address usage
ps022827-1212 p r e l i m i n a r y nonvolatile data storage z8 encore! xp ? f082a series product specification 176 nonvolatile data storage the z8 encore! xp f082a series devices contain a nonvolatile data storage (nvds) ele- ment of up to 128 bytes. this memory can perform over 100,000 write cycles. operation the nvds is implemented by special purpose z ilog software stored in areas of program memory, which are not user-accessible. these special-purpose routines use the flash memory to store the data. th e routines incorporate a dynami c addressing scheme to maxi- mize the write/erase endurance of the flash. different members of the z8 encore! xp f082a series feature multiple nvds array sizes; see the part selection guide section on page 2 for details. devices containing 8 kb of flash memory do not include the nvds feature. nvds code interface two routines are required to access the nvds: a write routine and a read routine. both of these routines are accessed with a call instruc tion to a predefined address outside of the user-accessible program memory. both the nvds address and data are single-byte values. because these routines disturb the working regi ster set, user code must ensure that any required working register values are preser ved by pushing them onto the stack or by changing the working register pointer just prior to nvds execution. during both read and write accesses to the nvds, interrupt service is not disabled. any interrupts that occur during the nvds executio n must take care not to disturb the working register and existing stack contents or el se the array may become corrupted. disabling interrupts before executing nvds operations is recommended. use of the nvds requires 15 bytes of availa ble stack space. also, the contents of the working register set are overwritten. for correct nvds operation, the flash frequency registers must be programmed based on the system clock frequency (see the flash operation timing using the flash frequency registers section on page 149 ). note:
ps022827-1212 p r e l i m i n a r y nvds code interface z8 encore! xp ? f082a series product specification 177 byte write to write a byte to the nvds array, the user code must first push the ad dress, then the data byte onto the stack. th e user code issues a call instruction to the address of the byte- write routine (0x10b3). at the re turn from the sub-routine, the write status byte resides in working register r0. the bit fields of this status byte are defined in table 106. the con- tents of the status byte are undefined for wr ite operations to illega l addresses. also, user code must pop the address and data bytes off the stack. the write routine uses 13 bytes of stack space in addition to the two bytes of address and data pushed by the user. su fficient memory must be available for this stack usage. because of the flash memory architecture, nv ds writes exhibit a nonuniform execution time. in general, a write takes 251 s (assuming a 20 mhz system clock). every 400 to 500 writes, however, a maintenance operation is n ecessary. in this rare occurrence, the write takes up to 61 ms to complete . slower system clock speeds result in proportionally higher execution times. nvds byte writes to invalid addresses (those exceeding the nvds array size) have no effect. illegal write operations have a 2 s execution time. table 106. write status byte bit 7 6 5 4 3 2 1 0 field reserved rcpy pf awe dwe default value 00000000 bit description [7:4] reserved these bits are reserved and must be programmed to 0000. [3] ? rcpy recopy subroutine executed a recopy subroutine was executed. these operati ons take significantly longer than a normal write operation. [2] ? pf power failure indicator a power failure or system reset occurred during the most recent attempted write to the nvds array. [1] ? awe address write error an address byte failure occurred during the mo st recent attempted write to the nvds array. [0] ? dwe data write error a data byte failure occurred during the most recent attempted write to the nvds array.
ps022827-1212 p r e l i m i n a r y nvds code interface z8 encore! xp ? f082a series product specification 178 byte read to read a byte from the nvds array, user co de must first push the address onto the stack. user code issues a call instruction to the address of the byte-read routine ( 0x1000 ). at the return from the sub-routine, the read byte resides in work ing register r0 and the read status byte resides in working register r1. the contents of the status byte are undefined for read operations to illegal addresses. also, the user code must pop the address byte off the stack. the read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user. sufficient memory must be available for this stack usage. because of the flash memory architecture, nvds reads exhibit a nonuniform execution time. a read operation takes between 44 ? s and 489 ? s (assuming a 20 mhz system clock). slower system clock speeds result in proportionally higher execution times. nvds byte reads from invalid addresses (those exceeding the nvds array size) return 0xff. illegal read operations have a 2 ? s execution time. the status byte returned by the nvds read routine is zero for successful read, as deter- mined by a crc check. if the status byte is nonzero, there was a corrupted value in the nvds array at the location being read. in this case, the value returned in r0 is the byte most recently written to the arra y that does not have a crc error. power failure protection the nvds routines employ e rror checking mechanisms to ensure a power failure endan- gers only the most recently written byte. byte s previously written to the array are not per- turbed. a system reset (such as a pin reset or watchdog timer reset) that occurs during a write operation also perturbs the byt e currently being written. all other bytes in the array are unperturbed. optimizing nvds memory usage for execution speed nvds read time can vary drastically. this discrepancy is a trade-off for minimizing the frequency of writes that require post-write page erases, as indicated in table 107. the nvds read time of address n is a function of the number of writes to addresses other than n since the most recent write to address n, pl us the number of writes since the most recent page erase. neglecting effects caused by page era ses and results caused by the initial con- dition in which the nvds is blank, a rule of thumb is that every write since the most recent page erase causes read times of unwritten addresses to increase by 1 ? s up to a max- imum of (511-nvds_size) ? s.
ps022827-1212 p r e l i m i n a r y nvds code interface z8 encore! xp ? f082a series product specification 179 if nvds read performance is critical to your software architecture, you can optimize your code for speed. try the first suggesti on below before attempting the second. 1. periodically refresh all addresses that are used. the optimal use of nvds in terms of speed is to rotate the writes evenly among all addresses planned to use, bringing all reads closer to the minimum read time. be cause the minimum read time is much less than the write time, however, actual sp eed benefits are not always realized. 2. use as few unique addresses as possible to optimize the impact of refreshing, plus minimize the requirement for it. table 107. nvds read time operation minimum latency maximum latency read (16 byte array) 875 9961 read (64 byte array) 876 8952 read (128 byte array) 883 7609 write (16 byte array) 4973 5009 write (64 byte array) 4971 5013 write (128 byte array) 4984 5023 illegal read 43 43 illegal write 31 31
ps022827-1212 p r e l i m i n a r y on-chip debugger z8 encore! xp ? f082a series product specification 180 on-chip debugger the z8 encore! xp f082a series devices contain an integrated on-chip debugger (ocd) that provides advanced debugging features including: ? single pin interface ? reading and writing of the register file ? reading and writing of program and data memory ? setting of breakpoints and watchpoints ? executing ez8 cpu instructions ? debug pin sharing with general-purpose inpu t-output function to maximize pins avail- able to the user (8 -pin product only) architecture the on-chip debugger consists of four primar y functional blocks: tr ansmitter, receiver, auto-baud detector/generator and debug controller. figure 23 displays the architecture of the on-chip debugger. figure 23. on-chip debugger block diagram auto-baud system clock transmitter receiver dbg pin debug controller ez8 tm cpu control detector/generator
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 181 operation this section describes the interface and mode s of operation of the on-chip debugger. ocd interface the on-chip debugger uses the dbg pin for co mmunication with an external host. this one-pin interface is a bidirectio nal, open-drain interface that transmits and receives data. data transmission is half-duplex, in that tr ansmit and receive cannot occur simultaneously. the serial data on the dbg pin is sent us ing the standard asynchronous data format defined in rs-232. this pin creates an inte rface from the z8 enco re! xp f082a series products to the serial port of a host pc using minimal external hardware.two different methods for connecting the dbg pin to an rs-232 interfa ce are displayed in figure 24 and figure 25. the recommended method is the buffered implementation displayed in figure 25. the dbg pin has a internal pull-up resistor which is sufficient for some appli- cations (for more details about the pull-up current, see the electrical characteristics chap- ter on page 226). for ocd operation at higher data rates or in noisy systems, an external pull-up resistor is recommended. for operation of the on-chip debugger, all power pins (v dd and av dd ) must be supplied with power and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and may require an external pull-up resistor to ensure proper operation. figure 24. interfacing the on-chip debugger?s dbg pin with an rs-232 interface; #1 of 2 caution: rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10 kohm schottky diode
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 182 debug mode the operating characteristics of the devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez8 cpu, unless directed by the ocd to ex- ecute specific instructions ? the system clock operates unless in stop mode ? all enabled on-chip peripherals operate unless in stop mode ? automatically exits halt mode ? constantly refreshes the wa tchdog timer, if enabled entering debug mode the operating characteristics of th e devices entering debug mode are: ? the device enters debug mode after the ez8 cpu executes a brk (breakpoint) in- struction ? if the dbg pin is held low during the final cl ock cycle of system reset, the part enters debug mode immediately (20-/28-pin products only) holding the dbg pin low for an additional 5000 (minimum) clock cycles after reset (making sure to account for any specified frequency erro r if using an internal oscillator) prevents a false interpretation of an autobaud sequence (see the ocd auto-baud detector/generator section on page 183). figure 25. interfacing the on-chip debugger?s dbg pin with an rs-232 interface; #2 of 2 rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10 k ? open-drain buffer note:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 183 ? if the pa2/reset pin is held low while a 32-bit key sequence is issued to the pa0/ dbg pin, the dbg feature is un locked. after releasing pa2/reset , it is pulled high. at this point, the pa0/dbg pin may be used to autobaud and cause the device to enter debug mode. see the ocd unlock sequence (8-pin devices only) section on page 185 . exiting debug mode the device exits debug mode foll owing any of these operations: ? clearing the dbgmode bit in th e ocd control register to 0 ? power-on reset ? voltage brown-out reset ? watchdog timer reset ? asserting the reset pin low to initiate a reset ? driving the dbg pin low while the device is in stop mode initiates a system reset ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character transmitted and received by the ocd consists of 1 start bit, 8 data bits (least-significant bit first) and 1 stop bit as displayed in figure 26. when responding to a request for data, the ocd may comm ence transmitting immediately after receiving the stop bit of an incoming fra me. therefore, when se nding the stop bit, the host must not actively drive the dbg pin high for more than 0.5 bit times. zilog recom- mends that, if possible, the ho st drives the dbg pin using an open drain output to avoid this issue. ocd auto-baud detector/generator to run over a range of baud rates (data bits per second) with various system clock frequen- cies, the on-chip debugger contains an auto -baud detector/generator. after a reset, the ocd is idle until it receives data. the ocd re quires that the first character sent from the figure 26. ocd data format startd0d1d2d3d4d5d6d7stop note:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 184 host is the character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data bits), framed between high bits. the auto-baud detector measures this period and sets the ocd baud rate generator accordingly. the auto-baud detector/generator is clocke d by the system clock. the minimum baud rate is the system clock frequency divided by 512. for optimal operation with asynchro- nous datastreams, the maximum recommended baud rate is the system clock frequency divided by 8. the maximum possible baud ra te for asynchronous datastreams is the sys- tem clock frequency divided by 4, but this th eoretical maximum is possible only for low noise designs with clean signals. table 108 lists minimum and recommended maximum baud rates for sample crystal frequencies. if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. reconfigure the auto-baud detector/generator by sending 80h . ocd serial errors the on-chip debugger can detect any of the following error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (ocd and ho st simultaneous transmissi on detected by the ocd) ? when the ocd detects one of these errors, it aborts any command currently in progress, transmits a four character long serial brea k back to the host and resets the auto-baud detector/generator. a framing error or tran smit collision may be caused by the host sending a serial break to the ocd. because of the open-drain natu re of the interface, returning a serial break break back to the host only extends the length of the serial break if the host releases the serial break early. the host transmits a serial break on the dbg pin when first connec ting to the z8 encore! xp f082a series devices or when recovering from an error. a serial break from the host resets the auto-baud generator/detector bu t does not reset the ocd control register. a table 108. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbps) recommended standard pc baud rate (bps) minimum baud rate (kbps) 20.0 2500.0 1,843,200 39 1.0 125.0 115,200 1.95 0.032768 (32 khz) 4.096 2,400 0.064
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 185 serial break leaves the device in debug mode if that is the current mode. the ocd is held in reset until the end of the serial brea k when the dbg pin returns high. because of the open-drain nature of the dbg pin, the host can send a serial break to the ocd even if the ocd is transmitting a character. ocd unlock sequence (8-pin devices only) because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the dbg pin. if this sequence is not completed during a system reset, then the pa0/ dbg pin functions only as a gpio pin. the following sequence unlocks the dbg pin: 1. hold pa2/reset low. 2. wait 5ms for the internal reset sequence to complete. 3. send the following bytes serially to the debug pin: dbg 80h (autobaud) dbg ebh dbg 5ah dbg 70h dbg cdh (32-bit unlock key) 4. release pa2/reset . the pa0/dbg pin is now identical in function to that of the dbg pin on the 20-/28-pin device. to enter debug mode, reautobaud and write 80h to the ocd control register (see the on-chip debugger commands section on page 186 ) . between steps 3 and 4 , there is an interval during which the 8-pin device is neither in re- set nor debug mode. if a device has been erased or has not yet been programmed, all program memory bytes contain ffh . the cpu interprets this value as an illegal instruc- tion; therefore some irregular behavior can occur before entering debug mode, and the register values after entering debug mode w ill differ from their specified reset values. however, none of these irregularities preven t the programming of flash memory. before beginning system debug, zilog recommends that some legal code be programmed into the 8-pin device and that a reset occurs. breakpoints execution breakpoints are generated using the brk instruction (opcode 00h ). when the ez8 cpu decodes a brk instruction, it signal s the on-chip debugger. if breakpoints are enabled, the ocd enters debug mode and idles the ez8 cpu. if breakpoints are not caution:
ps022827-1212 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f082a series product specification 186 enabled, the ocd ignores the brk signal and the brk instruction operates as an nop instruction. breakpoints in flash memory the brk instruction is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the required break address, overwriting the current instruction. to remove a breakpoi nt, the corresponding page of flash memory must be erased an d reprogrammed with the original data. runtime counter the on-chip debugger contains a 16-bit run time counter. it counts system clock cycles between breakpoints. the counter starts co unting when the on-chip debugger leaves debug mode and stops counting when it ente rs debug mode again or when it reaches the maximum count of ffffh . on-chip debugger commands the host communicates to the on-chip debugger by sending ocd commands using the dbg interface. during normal operation, on ly a subset of the ocd commands are avail- able. in debug mode, all ocd commands be come available unless the user code and control registers are protected by programming the flash read protect option bit (frp). the flash read protect option bit prevents the code in memory from being read out of the z8 encore! xp f082a series device. when th is option is enabled, several of the ocd commands are disabled. see table 109. table 110 on page 191 is a summary of the on-chip debugger commands. each ocd com- mand is described in further detail in the bulle ted list following this table. table 110 also indicates those commands that operate when the device is not in debug mode (normal operation) and those commands that are disa bled by programming the flash read protect option bit. table 109. debug command enable/disable debug command command byte enabled when not in debug mode? disabled by flash read protect option bit read ocd revision 00h yes ? reserved 01h ? ? read ocd status register 02h yes ? read runtime counter 03h ? ? write ocd control register 04h yes cannot clear dbgmode bit. read ocd control register 05h yes ?
ps022827-1212 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f082a series product specification 187 in the list of ocd commands that follows, data and commands sent from the host to the on-chip debugger are identified by dbg command/data . data sent from the on- chip debugger back to th e host is identified by dbg : data . read ocd revision (00h). the read ocd revision comman d determines the version of the on-chip debugger. if ocd commands are adde d, removed, or changed, this revision number changes. dbg 00h dbg : ocdrev[15:8] (major revision number) dbg : ocdrev[7:0] (minor revision number) read ocd status register (02h). the read ocd status register command reads the ocdstat register. dbg 02h dbg : ocdstat[7:0] read runtime counter (03h). the runtime counter counts system clock cycles in between breakpoints. the 16-bit runtime counter counts up from 0000h and stops at the maximum count of ffffh . the runtime counter is overwritten during the write memory, write program counter 06h ? disabled. read program counter 07h ? disabled. write register 08h ? only writes of the flash memory control registers are allowed. additionally, only the mass erase command is allowed to be written to the flash control register. read register 09h ? disabled. write program memory 0ah ? disabled. read program memory 0bh ? disabled. write data memory 0ch ? yes. read data memory 0dh ? ? read program memory crc 0eh ? ? reserved 0fh ? ? step instruction 10h ? disabled. stuff instruction 11h ? disabled. execute instruction 12h ? disabled. reserved 13h?ffh ? ? table 109. debug command enable/disable (continued) debug command command byte enabled when not in debug mode? disabled by flash read protect option bit
ps022827-1212 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f082a series product specification 188 read memory, write register, read register, read memory crc, step instruction, stuff instruction and execute instruction commands. dbg 03h dbg : runtimecounter[15:8] dbg : runtimecounter[7:0] write ocd control register (04h). the write ocd control register command writes the data that follows to the ocdctl register . when the flash read protect option bit is enabled, the dbgmode bit ( ocdctl [7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating mode is to reset the device. dbg 04h dbg ocdctl[7:0] read ocd control register (05h). the read ocd control regi ster command reads the value of the ocdctl register. dbg 05h dbg : ocdctl[7:0] write program counter (06h). the write program counter command writes the data that follows to the ez8 cpu?s program coun ter (pc). if the device is not in debug mode or if the flash read protect option bit is enabled, the progra m counter (pc) values are discarded. dbg 06h dbg programcounter[15:8] dbg programcounter[7:0] read program counter (07h). the read program counter co mmand reads the value in the ez8 cpu?s program counter (pc). if the device is not in debug mode or if the flash read protect option bit is en abled, this command returns ffffh . dbg 07h dbg : programcounter[15:8] dbg : programcounter[7:0] write register (08h). the write register command writes data to the register file. data can be written 1?256 bytes at a time (256 bytes can be written by setting size to 0). if the device is not in debug mode, the address and data values are discarded. if the flash read protect option bit is enabled, only writes to the flash control registers are allowed and all other register write data values are discarded. dbg 08h dbg {4?h0,register address[11:8]} dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes
ps022827-1212 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f082a series product specification 189 read register (09h). the read register command reads data from the register file. data can be read 1?256 bytes at a time (256 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect op tion bit is enabled, this com- mand returns ffh for all the data values. dbg 09h dbg {4?h0,register address[11:8] dbg register address[7:0] dbg size[7:0] dbg : 1-256 data bytes write program me mory (0ah). the write program memory command writes data to program memory. this command is equivalent to the ldc and ldci instructions. data can be written 1?65536 bytes at a time (65536 bytes can be written by setting size to 0). the on-chip flash controller must be written to and unlocked for the programming opera- tion to occur. if the flash controller is not unlo cked, the data is discarded. if the device is not in debug mode or if the flash read protect option bit is enabled, the data is dis- carded. dbg 0ah dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes read program memory (0bh). the read program memory command reads data from program memory. this command is equivalent to the ldc and ldci instructions. data can be read 1?65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect op tion bit is enabled, this com- mand returns ffh for the data. dbg 0bh dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg : 1-65536 data bytes write data memory (0ch). the write data memory comman d writes data to data mem- ory. this command is equivalent to the ld e and ldei instructions. data can be written 1?65536 bytes at a time (65536 bytes can be written by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, the data is dis- carded. dbg 0ch dbg data memory address[15:8] dbg data memory address[7:0]
ps022827-1212 p r e l i m i n a r y on-chip debugger commands z8 encore! xp ? f082a series product specification 190 dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes read data memory (0dh). the read data memory comm and reads from data memory. this command is equivalent to the lde and ldei instructi ons. data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg : 1-65536 data bytes read program memory crc (0eh). the read program me mory crc command com- putes and returns the cyclic redundancy ch eck (crc) of program memory using the 16- bit crc-ccitt polynomial. if the device is no t in debug mode, this command returns ffffh for the crc value. unlike most other oc d read commands, there is a delay from issuing of the command until the ocd returns the data. the ocd reads the program memory, calculates the crc value and returns the result. the delay is a function of the program memory size and is approximately equa l to the system clock period multiplied by the number of bytes in the program memory. dbg 0eh dbg : crc[15:8] dbg : crc[7:0] step instruction (10h). the step instruction command st eps one assembly instruction at the current program counter (p c) location. if the device is not in debug mode or the flash read protect option bit is enab led, the ocd ignores this command. dbg 10h stuff instruction (11h). the stuff instruction command steps one assembly instruction and allows specification of the first byte of the instruction. the rema ining 0-4 bytes of the instruction are read from program memory. th is command is useful for stepping over instructions where the first byte of the instru ction has been overwritten by a breakpoint. if the device is not in debug mode or the flas h read protect option bit is enabled, the ocd ignores this command. dbg 11h dbg opcode[7:0] execute instruction (12h). the execute instruction command allows sending an entire instruction to be executed to the ez8 cpu. th is command can also st ep over breakpoints. the number of bytes to send fo r the instruction depends on the opcode. if the device is not
ps022827-1212 p r e l i m i n a r y on-chip debugger control register z8 encore! xp ? f082a series product specification 191 in debug mode or the flash read protect option bit is enabled, th is command reads and discards one byte. dbg 12h dbg 1-5 byte opcode on-chip debugger control register definitions this section describes the features of the on -chip debugger control and status registers. ocd control register the ocd control register controls the state of the on-chip debugger. this register is used to enter or exit debu g mode and to enable the brk instruction. it can also reset the z8 encore! xp f082a series device. a reset and stop function can be achieved by writing 81h to this register. a reset and go function can be achieved by writing 41h to this register. if the device is in debug mode, a run function can be implemented by writing 40h to this register. table 110. ocd control register (ocdctl) bit 7 6 5 4 3 2 1 0 field dbgmode brken dbgack reserved rst reset 0 0000000 r/w r/wr/wr/wrrrrr/w bit description [7] dbgmode debug mode the device enters debug mode when this bi t is 1. when in debug mode, the ez8 cpu stops fetching new instructions. clearing this bit causes the ez8 cpu to restart. this bit is automatically set when a brk instruction is decoded and breakpoints are enabled. if the flash read protect option bit is enabled, this bit can only be cleared by resetting the device. it cannot be written to 0. 0 = the z8 encore! xp f082a series device is operating in normal mode. 1 = the z8 encore! xp f082a series device is in debug mode. [6] brken breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h ). by default, breakpoints are disabled and the brk instruction behaves similar to an nop instruction. if this bit is 1, when a brk instruction is decoded, the dbgmode bit of the ocdctl register is automati- cally set to 1. 0 = breakpoints are disabled. 1 = breakpoints are enabled.
ps022827-1212 p r e l i m i n a r y on-chip debugger control register z8 encore! xp ? f082a series product specification 192 ocd status register the ocd status register reports status inform ation about the current state of the debugger and the system. [5] ? dbgack debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, the ocd sends a debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. [4:1] reserved these bits are reserved and must be programmed to 0000. [0] ? rst reset setting this bit to 1 resets the z8f04xa family device. the device goes through a normal power-on reset sequence with the exception that the on-chip debugger is not reset. this bit is automatically cleared to 0 at the end of reset. 0 = no effect. 1 = reset the flash read protect option bit device. table 111. ocd status register (ocdstat) bit 7 6 5 4 3 2 1 0 field dbg halt frpenb reserved reset 00000000 r/w rrrrrrrr bit description [7] ? dbg debug status 0 = normal mode. 1 = debug mode. [6] ? halt halt mode 0 = not in halt mode. 1 = in halt mode. [5] ? frpenb flash read protect option bit enable 0 = frp bit enabled, that allows disabling of many ocd commands. 1 = frp bit has no effect. [4:0] reserved these bits are reserved and must be programmed to 00000. bit description (continued)
ps022827-1212 p r e l i m i n a r y oscillator control z8 encore! xp ? f082a series product specification 193 oscillator control the z8 encore! xp f082a series devices uses five possible clocking schemes, each user- selectable: ? internal precision trimmed rc oscillator (ipo) ? on-chip oscillator using off-chip crystal or resonator ? on-chip oscillator usin g external rc network ? external clock drive ? on-chip low power watchdog timer oscillator ? clock failure detection circuitry ? in addition, z8 encore! xp f082a series de vices contain clock failure detection and recovery circuitry, allowing continued oper ation despite a failure of the system clock oscillator. operation this chapter discusses the logic used to select the system clock and handle primary oscil- lator failures. system clock selection the oscillator control block selects from the av ailable clocks. table 11 2 details each clock source and its usage.
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 194 unintentional accesses to the o scillator control register can actually stop the chip by switching to a nonfunctioning oscillator. to prevent this condition, the oscillator control block employs a register unlocking/locking scheme. osc control register unlocking/locking to write the oscillator control register, un lock it by making two writes to the oscctl register with the values e7h followed by 18h . a third write to the oscctl register changes the value of the actual register and retu rns the register to a locked state. any other sequence of oscillator control register writes has no effect. the values written to unlock the register must be ordered correctly, but are not necessarily consecutive. it is possible to write to or read from other registers within the unlockin g/locking operation. table 112. oscillator c onfiguration and selection clock source characteristics required setup internal precision rc oscillator ? 32.8 khz or 5.53 mhz ? high accuracy ? no external components required ? unlock and write oscillator control register (oscctl) to enable and select oscillator at either 5.53 mhz or 32.8 khz external crystal/ resonator ? 32 khz to 20 mhz ? very high accuracy (dependent on crystal or resonator used) ? requires external components ? configure flash option bits for correct external oscillator mode ? unlock and write oscctl to enable crystal oscillator, wait for it to stabilize and select as system clock (if the xtldis option bit has been deas- serted, no waiting is required) external rc oscilla- tor ? 32 khz to 4 mhz ? accuracy dependent on external com- ponents ? configure flash option bits for correct external oscillator mode ? unlock and write oscctl to enable crystal oscillator and select as system clock external clock drive ? 0 to 20 mhz ? accuracy dependent on external clock source ? write gpio registers to configure pb3 pin for external clock function ? unlock and write oscctl to select external system clock ? apply external clock signal to gpio internal watchdog timer oscillator ? 10 khz nominal ? low accuracy; no external compo- nents required ? very low power consumption ? enable wdt if not enabled and wait until wdt oscillator is operating ? unlock and write oscillator control register (oscctl) to enable and select oscillator caution:
ps022827-1212 p r e l i m i n a r y operation z8 encore! xp ? f082a series product specification 195 when selecting a new clock sour ce, the system clock oscillato r failure detection circuitry and the watchdog timer oscillator failure ci rcuitry must be di sabled. if sofen and wofen are not disabled prior to a clock switc h-over, it is possible to generate an inter- rupt for a failure of either oscillator. the failure detection circuitry can be enabled any- time after a successful write of oscsel in the oscctl register. the internal precision oscillator is enabled by default. if the user code changes to a differ- ent oscillator, it may be appr opriate to disable the ipo fo r power savings. disabling the ipo does not occur automatically. clock failure detection and recovery should an oscillator or timer fail, there ar e methods of recovery, as this section describes. system clock osci llator failure the z8f04xa family devices can generate no nmaskable interrupt-like events when the primary oscillator fails. to maintain system fu nction in this situatio n, the clock failure recovery circuitry automatica lly forces the watchdog timer o scillator to drive the system clock. the watchdog timer oscillator must be enabled to allow th e recovery. although this oscillator runs at a much slower speed than the original system clock, the cpu contin- ues to operate, allowing execution of a cloc k failure vector and software routines that either remedy the oscillator failure or issue a failure alert. this au tomatic switch-over is not available if the watchdog timer is selected as the system clock oscillator. it is also unavailable if the watchdog timer oscillator is disabled, though it is not necessary to enable the watchdog timer reset function (see the watchdog timer chapter on page 93). the primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1 khz 50%. if an external signal is selected as the system oscillator, it is pos- sible that a very slow but nonfailing clock can generate a failure condition. under these conditions, do not enable the cl ock failure circuitry (sofen must be deasserted in the oscctl register). watchdog timer failure in the event of a watchdog timer oscillator failure, a similar nonmaskable interrupt-like event is issued. this event does not trigger an attendant clock switch-over, but alerts the cpu of the failure. after a watchdog timer failu re, it is no longer possible to detect a pri- mary oscillator failure. the failure detection circuitry does not function if the watchdog timer is used as the system clock oscillator or if the watchdog timer oscillator has been disabled. for either of these cases, it is necessary to disable the detection circuitry by deas- serting the wdfen bit of the oscctl register. the watchdog timer oscillator fa ilure detection circuit counts system clocks while look- ing for a watchdog timer clock. the logic coun ts 8004 system clock cycles before deter- mining that a failure has occurred. the system clock rate determines the speed at which
ps022827-1212 p r e l i m i n a r y oscillator control register definitions z8 encore! xp ? f082a series product specification 196 the watchdog timer failure can be detected. a ve ry slow system clock results in very slow detection times. it is possible to disable the clock failure detection circuitry and all functioning clock sources. in this case, the z8 encore! xp f082a series device ceases functioning and can only be recovered by power-on-reset. oscillator control register definitions the oscillator control register (oscctl) enables/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry and selects the primary oscillator, which becomes th e system clock. the oscillator control register must be unlo cked before writing. unlock the oscillator control register by writing the two-step sequence e7h followed by 18h . the register is locked at successful completion of a register write to the oscctl. table 113. oscillator c ontrol register (oscctl) bit 7 6 5 4 3 2 1 0 field inten xtlen wdten sofen wdfen scksel reset 10100000 r/w r/wr/wr/wr/wr/wr/wr/wr/w address f86h bit description [7] ? inten internal precision oscillator enable 1 = internal precision oscillator is enabled. 0 = internal precision oscillator is disabled. [6] ? xtlen crystal oscillator enable; this setting overrides the gpio register control for pa0 and pa1 1 = crystal oscillator is enabled. 0 = crystal oscillator is disabled. [5] ? wdten watchdog timer oscillator enable 1 = watchdog timer oscillator is enabled. 0 = watchdog timer os cillator is disabled. [4] ? sofen system clock oscillator failure detection enable 1 = failure detection and recovery of system clock oscillator is enabled. 0 = failure detection and recovery of system clock oscillator is disabled. caution:
ps022827-1212 p r e l i m i n a r y oscillator control register definitions z8 encore! xp ? f082a series product specification 197 [3] ? wdfen watchdog timer oscillator failure detection enable 1 = failure detection of watchd og timer oscillator is enabled. 0 = failure detection of watchdog timer oscillator is disabled. [2:0] ? scksel system clock oscillator select 000 = internal precision oscillator func tions as system clock at 5.53 mhz. 001 = internal precision oscillator f unctions as system clock at 32 khz. 010 = crystal oscillator or external rc oscillator functions as system clock. 011 = watchdog timer oscilla tor functions as system. 100 = external clock signal on pb3 functions as system clock. 101 = reserved. 110 = reserved. 111 = reserved. bit description (continued)
ps022827-1212 p r e l i m i n a r y crystal oscillator z8 encore! xp ? f082a series product specification 198 crystal oscillator the products in the z8 encore! xp f082a series contain an on-chip crystal oscillator for use with external crystals with 32 khz to 20 mhz frequencies. in addition, the oscillator supports external rc networks with oscillatio n frequencies up to 4 mhz or ceramic reso- nators with frequencies up to 8 mhz. the on-chip crystal oscilla tor can be used to generate the primary system clock for the internal ez8 cpu and the majority of the on-chip periph- erals. alternatively, the x in input pin can also accept a cmos-level clock input signal (32 khz?20 mhz). if an external clock generator is used, the x out pin must be left uncon- nected. the z8 encore! xp f082a series products do not contain an internal clock divider. the frequency of the signal on the x in input pin determines the frequency of the system clock. although the x in pin can be used as an input for an external clock generator, the clkin pin is better suited for such use (see the system clock selection section on page 193). operating modes the z8 encore! xp f082a series prod ucts support four oscillator modes: ? minimum power for use with very low frequency crystals (32 khz ? 1 mhz) ? medium power for use with medium frequency crystals or ceramic resonators (0.5 mhz to 8 mhz) ? maximum power for use with high frequ ency crystals (8 mhz to 20 mhz) ? on-chip oscillator configured for use with external rc networks (<4 mhz) ? the oscillator mode is selected via u ser-programmable flash option bits. see the flash option bits chapter on page 159 for information. crystal oscillator operation the xtldis flash option bit controls whether the crystal oscillator is enabled during reset. the crystal may later be disabled after reset if a new oscillato r has been selected as the system clock. if the crys tal is manually enabled afte r reset through the oscctl reg- ister, the user code must wait at least 1000 crystal oscillator cycles for the crystal to stabi- lize. after this, the crystal oscillator may be selected as the system clock. note:
ps022827-1212 p r e l i m i n a r y cry stal oscillator operation z8 encore! xp ? f082a series product specification 199 the stabilization time varies depending on the crystal, resonator or feedback network used. see table 115 for transconductance valu es to compute oscillator stabilization times. figure 27 displays a recommended configurat ion for connection with an external funda- mental-mode, parallel-resonant crystal operat ing at 20 mhz. recommended 20 mhz crys- tal specifications are provided in table 114. printed circuit board layouts must add no more than 4 pf of stray ca pacitance to either the x in or x out pins. if oscillation does not occur, reduce the values of capac itors c1 and c2 to decrease loading. figure 27. recommended 20 mhz crystal oscillator configuration note: c2 = 15 pf c1 = 15 pf crystal x out x in on-chip oscillator
ps022827-1212 p r e l i m i n a r y cry stal oscillator operation z8 encore! xp ? f082a series product specification 200 table 114. recommended crystal oscillator specifications parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s ) 60 w maximum load capacitance (c l )30 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum table 115. transconductance values for low, medium and high gain operating modes mode crystal frequency range function transconductance (ma/v) (use this range for calculations) low gain* 32 khz ? 1 mhz low power/frequency applications 0.02 0.04 0.09 medium gain* 0.5 mhz ? 10 mhz medium power/frequency applications 0.84 1.7 3.1 high gain* 8 mhz ? 20 mhz high power/frequency applications 1.1 2.3 4.2 note: *printed circuit board layouts must not add more than 4 pf of stray capacitance to either the x in or x out pins. if no oscillation occurs, reduce the values of t he capacitors c1 and c2 to decrease the loading.
ps022827-1212 p r e l i m i n a r y oscillator operation with an external rc z8 encore! xp ? f082a series product specification 201 oscillator operation with an external rc network figure 28 displays a recommended configuratio n for connection with an external resistor- capacitor (rc) network. an external resistance value of 45 k ? is recommended for osc illator operation with an external rc network. the minimum resistance value to ensure operation is 40 k ??? the typical oscillator frequency can be esti mated from the values of the resistor ( r in k ? ) and capacitor ( c in pf) elements usi ng the following equation: figure 29 displays the typical (3.3 v and 25c) oscillator frequency as a function of the capacitor (c, in pf) employed in the rc network assuming a 45 k ? external resistor. for very small values of c, the parasitic capacitance of the oscillator x in pin and the printed circuit board must be included in the estimation of the oscillator frequency. it is possible to operate the rc oscillator usin g only the parasitic ca pacitance of the pack- age and printed circuit board. to minimize sensitivity to external parasitics, external capacitance values in excess of 20 pf are recommended. figure 28. connecting the on-chip osci llator to an external rc network c x in r vdd oscillator frequency (khz) 1 6 ? 10 0.4 r c ?? ?? 4c ? ?? + --------------------------------------- ---------------- =
ps022827-1212 p r e l i m i n a r y oscillator operation with an external rc z8 encore! xp ? f082a series product specification 202 when using the external rc oscillator mode , the oscillator can stop oscillating if the power supply drops below 2.7 v, but before the power supply drops to the voltage brown- out threshold. the oscillator resumes oscilla tion when the supply voltage exceeds 2.7 v. figure 29. typical rc oscillator frequency as a function of the external capacitance with a 45 k ? resistor 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 c (pf) frequency (khz) caution:
ps022827-1212 p r e l i m i n a r y int ernal precision oscillator z8 encore! xp ? f082a series product specification 203 internal precision oscillator the internal precision oscillator (ipo) is de signed for use without external components. you can either manually trim the oscillator for a nonstandard frequen cy or use the auto- matic factory-trimmed version to achieve a 5.53 mhz frequency. ipo features include: ? on-chip rc oscillator that does not require external components ? output frequency of either 5.53 mhz or 32.8 khz (contains both a fast and a slow mode) ? trimmed through flash option bits with user override ? elimination of crystals or ceramic resonators in applications where very high timing accuracy is not required operation an 8-bit trimming register, incorporated into the design, compensates for absolute varia- tion of oscillator frequency. once trimmed the o scillator frequency is stable and does not require subsequent calibration. trimming is performed during manufacturing and is not necessary for you to repeat unless a frequen cy other than 5.53 mhz (fast mode) or 32.8 khz (slow mode) is required. this trimming is done at +30oc and a supply voltage of 3.3 v, so accuracy of this operating point is optimal. if not used, the ipo can be disabled by the oscillator control register (see the oscillator control register definitions section on page 196 ). by default, the oscillator frequency is set by the factory trim value stored in the write-pro- tected flash information page. however, the user code can ov erride these trim values as described in the trim bit address space section on page 165. select one of two frequencies for the oscillator (5.53 mhz and 32.8 khz) using the osc- sel bits in the the oscillator control chapter on page 193.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction set z8 encore! xp ? f082a series product specification 204 ez8 cpu instruction set this chapter describes the following feat ures of the ez8 cpu instruction set: assembly language programming introduction : see page 204 assembly language syntax : see page 205 ez8 cpu instruction notation : see page 206 ez8 cpu instruction classes : see page 207 ez8 cpu instruction summary : see page 212 assembly language programming introduction the ez8 cpu assembly language provides a me ans for writing an application program without concern for actual memory addresses or machine instruction formats. a program written in assembly language is called a sour ce program. assembly language allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to represent the inst ructions themselves. th e opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called state- ments. each statement can contain labe ls, operations, operands and comments. labels can be assigned to a particular instru ction step in a source program. the label iden- tifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example.
ps022827-1212 p r e l i m i n a r y assembly language syntax z8 encore! xp ? f082a series product specification 205 assembly language s ource program example assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. after assembly, the obj ect code usually has the operands in the order ?source, destination?, but ordering is opcode-dependent. the fol- lowing instruction examples illust rate the format of some ba sic assembly instructions and the resulting object code produced by the assembler. this binary format must be followed if manual program coding is preferred or if you intend to implement your own assembler. example 1. if the contents of registers 43h and 08h are added and the result is stored in 43h , the assembly syntax and resulting object code is: example 2. in general, when an instruction format requires an 8-bit register address, that address can specify any regist er location in the range 0?255 or, using escaped mode addressing, a working register r0?r15. if th e contents of register 43h and working register r8 are added and the result is stored in 43h , the assembly syntax and resulting object code is: jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the destination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, #%01 ; another load (ld) instruction with two operands. ; the first operand, extend ed mode register address 234h , ; identifies the destination. the second operand, immediate data ; value 01h , is the source. the value 01h is written into the ; register at address 234h. table 116. assembly language syntax example 1 assembly language code add 43h, 08h (add dst, src) object code 04 08 43 (opc src, dst) table 117. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst)
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction notation z8 encore! xp ? f082a series product specification 206 register file size varies depending on the de vice type. see the device-specific z8 encore! xp product specification to determine th e exact register file range available. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, the operands, condition codes, status flags and address modes are repr esented by a notational shorthand that is described in table 118. . table 118. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? refer to the condition codes section in the ez8 cpu core user manual (um0128) . da direct address addrs represents a number in the range 0000h to ffffh. er extended addressing register reg reg. represents a number in the range of 000h to fffh. im immediate data #data data is a number between 00h to ffh. ir indirect working register @rn n = 0?15. ir indirect register @reg reg. repres ents a number in the range of 00h to ffh. irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14. irr indirect register pair @reg reg. represents an even number in the range 00h to feh. p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0 ? 15. r register reg reg. represents a number in the range of 00h to ffh. ra relative address x x represents an index in the range of +127 to ? 128 which is an offset relative to the address of the next instruction. rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14. rr register pair reg reg. represents an even number in the range of 00h to feh.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f082a series product specification 207 table 119 lists additional symbols that are us ed throughout the in struction summary and instruction set description sections. assignment of a value is indicated by an arrow, as shown in the following example. dst dst + src this example indicates that the source data is added to the destina tion data; the result is stored in the destination location. ez8 cpu instruction classes ez8 cpu instructions can be divided fu nctionally into the following groups: ? arithmetic ? bit manipulation vector vector address vector vector represents a number in the range of 00h to ffh. x indexed #index the register or register pair to be indexed is off- set by the signed index value (#index) in a +127 to ?128 range. table 119. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix table 118. notational shorthand (continued) notation description operand range
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f082a series product specification 208 ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift ? tables 120 through 127 list the instructions belonging to each group and the number of operands required for each instruction. some in structions appear in more than one table as these instruction can be considered as a subset of more than one ca tegory. within these tables, the source operand is identified as src , the destination operand is dst and a condi- tion code is cc . table 120. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word mult dst multiply sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract using extended addressing
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f082a series product specification 209 table 121. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test comp lement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 122. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto- increment addresses ldei dst, src load external data to/from data memory and auto- increment addresses table 123. cpu control instructions mnemonic operands instruction atm ? atomic execution ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f082a series product specification 210 rcf ? reset carry flag scf ? set carry flag srp src set regi ster pointer stop ? stop mode wdt ? watchdog timer refresh table 124. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto- increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/from data memory and auto- increment addresses ldwx dst, src load word using extended addressing ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing table 125. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or orx dst, src logical or using extended addressing xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 123. cpu control instructions (continued) mnemonic operands instruction
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction classes z8 encore! xp ? f082a series product specification 211 table 126. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decrement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap table 127. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic srl dst shift right logical swap dst swap nibbles
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 212 ez8 cpu instruction summary table 128 summarizes the ez8 cpu instruc tions. the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch and the number of cpu clock cycles required for the instruction execution. table 128. ez8 cpu instruction summary assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h adc dst, src dst ? dst + src + c r r 12 * * * * 0 * 2 3 rir 13 2 4 rr 14 3 3 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst ? dst + src + c er er 18 * * * * 0 * 4 3 er im 19 4 3 add dst, src dst ? dst + src r r 02 * * * * 0 * 2 3 rir 03 2 4 rr 04 3 3 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst ? dst + src er er 08 * * * * 0 * 4 3 er im 09 4 3 note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 213 and dst, src dst ? dst and src r r 52 ? * * 0 ? ? 2 3 rir 53 2 4 rr 54 3 3 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst ? dst and src er er 58 ? * * 0 ? ? 4 3 er im 59 4 3 atm block all interrupt and dma requests during execution of the next 3 instructions 2f ?????? 1 2 bclr bit, dst dst[bit] ? 0 r e2 ?????? 2 2 bit p, bit, dst dst[bit] ? p r e2 ?????? 2 2 brk debugger break 00 ? ? ? ? ? ? 1 1 bset bit, dst dst[bit] ? 1 r e2 ?????? 2 2 bswap dst dst[7:0] ? dst[0:7] r d5 x * * 0 ? ? 2 2 btj p, bit, src, dst if src[bit] = p ? pc ? pc + x r f6 ?????? 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 ? pc ? pc + x r f6 ?????? 3 3 ir f7 3 4 btjz bit, src, dst if src[bit] = 0 ? pc ? pc + x r f6 ?????? 3 3 ir f7 3 4 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 214 call dst sp ? sp -2 ? @sp ? pc ? pc ? dst irr d4 ?????? 2 6 da d6 3 3 ccf c ? ~c ef *?????- 1 2 clr dst dst ? 00h r b0 ? ? ? ? ? ? 2 2 ir b1 2 3 com dst dst ? ~dst r 60 ? * * 0 ? ? 2 2 ir 61 2 3 cp dst, src dst - src r r a2 * * * * ? ? 2 3 rir a3 2 4 rr a4 3 3 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 * * * * ? ? 3 3 rir1f a3 3 4 rr1f a4 4 3 rir1f a5 4 4 rim1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 * * * * ? ? 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 * * * * ? ? 4 3 er im a9 4 3 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 215 da dst dst ? da(dst) r 40 * * * x ? ? 2 2 ir 41 2 3 dec dst dst ? dst - 1 r 30 ? * * * ? ? 2 2 ir 31 2 3 decw dst dst ? dst - 1 rr 80 ? * * * ? ? 2 5 irr 81 2 6 di irqctl[7] ? 0 8f ?????? 1 2 djnz dst, ra dst ? dst ? 1 ? if dst ? 0 ? pc ? pc + x r 0a-fa ?????? 2 3 ei irqctl[7] ? 1 9f ?????? 1 2 halt halt mode 7f ? ? ? ? ? ? 1 2 inc dst dst ? dst + 1 r 20 ? * * ? ? ? 2 2 ir 21 2 3 r0e-fe 12 incw dst dst ? dst + 1 rr a0 ? * * * ? ? 2 5 irr a1 2 6 iret flags ? @sp ? sp ? sp + 1 ? pc ? @sp ? sp ? sp + 2 ? irqctl[7] ? 1 bf ****** 1 5 jp dst pc ? dst da 8d ?????? 3 2 irr c4 2 3 jp cc, dst if cc is true ? pc ? dst da 0d-fd ?????? 3 2 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 216 jr dst pc ? pc + x da 8b ?????? 2 2 jr cc, dst if cc is true ? pc ? pc + x da 0b-fb ?????? 2 2 ld dst, rc dst ? src r im 0c-fc ?????? 2 2 rx(r) c7 3 3 x(r) r d7 3 4 rir e3 2 3 rr e4 3 2 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 ldc dst, src dst ? src r irr c2 ?????? 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst ? src ? r ? r + 1 ? rr ? rr + 1 ir irr c3 ?????? 2 9 irr ir d3 2 9 lde dst, src dst ? src r irr 82 ?????? 2 5 irr r 92 2 5 ldei dst, src dst ? src ? r ? r + 1 ? rr ? rr + 1 ir irr 83 ?????? 2 9 irr ir 93 2 9 ldwx dst, src dst ? src er er 1fe8 ?????? 5 4 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 217 ldx dst, src dst ? src r er 84 ?????? 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst ? src + x r x(r) 98 ?????? 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] ? ? dst[15:8] * dst[7:0] rr f4 ?????? 2 8 nop no operation 0f ? ? ? ? ? ? 1 2 or dst, src dst ? dst or src r r 42 ? * * 0 ? ? 2 3 rir 43 2 4 rr 44 3 3 rir 45 3 4 rim 46 3 3 ir im 47 3 4 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 218 orx dst, src dst ? dst or src er er 48 ? * * 0 ? ? 4 3 er im 49 4 3 pop dst dst ? @sp ? sp ? sp + 1 r 50 ?????? 2 2 ir 51 2 3 popx dst dst ? @sp sp ? sp + 1 er d8 ?????? 3 2 push src sp ? sp ? 1 @sp ? src r 70 ?????? 2 2 ir 71 2 3 im if70 3 2 pushx src sp ? sp ? 1 ? @sp ? src er c8 ?????? 3 2 rcf c ? 0 cf 0????? 1 2 ret pc ? @sp ? sp ? sp + 2 af ?????? 1 4 rl dst r 90 * * * * ? ? 2 2 ir 91 2 3 rlc dst r 10 * * * * ? ? 2 2 ir 11 2 3 rr dst r e0 ****?? 2 2 ir e1 2 3 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1. d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 219 rrc dst r c0 * * * * ? ? 2 2 ir c1 2 3 sbc dst, src dst ? dst ? src - c r r 32 * * * * 1 * 2 3 rir 33 2 4 rr 34 3 3 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst ? dst ? src - c er er 38 * * * * 1 * 4 3 er im 39 4 3 scf c ? 1 df 1????? 1 2 sra dst r d0 * * * 0 ? ? 2 2 ir d1 2 3 srl dst r 1f c0 * * 0 * ? ? 3 2 ir 1f c1 3 3 srp src rp ? src im 01 ?????? 2 2 stop stop mode 6f ?????? 1 2 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1. d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 220 sub dst, src dst ? dst ? src r r 22 * * * * 1 * 2 3 rir 23 2 4 rr 24 3 3 rir 25 3 4 rim 26 3 3 ir im 27 3 4 subx dst, src dst ? dst ? src er er 28 * * * * 1 * 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x ? ? 2 2 ir f1 2 3 tcm dst, src (not dst) and src r r 62 ? * * 0 ? ? 2 3 rir 63 2 4 rr 64 3 3 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 ? * * 0 ? ? 4 3 er im 69 4 3 tm dst, src dst and src r r 72 ? * * 0 ? ? 2 3 rir 73 2 4 rr 74 3 3 rir 75 3 4 rim 76 3 3 ir im 77 3 4 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps022827-1212 p r e l i m i n a r y ez8 cpu instruction summary z8 encore! xp ? f082a series product specification 221 tmx dst, src dst and src er er 78 ? * * 0 ? ? 4 3 er im 79 4 3 trap vector sp ? sp ? 2 ? @sp ? pc ? sp ? sp ? 1 ? @sp ? flags ? pc ? @vector vector f2 ?????? 2 6 wdt 5f ?????? 1 2 xor dst, src dst ? dst xor src r r b2 ? * * 0 ? ? 2 3 rir b3 2 4 rr b4 3 3 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst ? dst xor src er er b8 ? * * 0 ? ? 4 3 er im b9 4 3 table 128. ez8 cpu instruction summary (continued) assembly ? mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycle s instr. cycle s dst src c z s v d h note: flags notation: * = value is a function of the result of the operation. ? ? = unaffected. ? x = undefined. 0 = reset to 0. ? 1 = set to 1.
ps022827-1212 p r e l i m i n a r y opcode maps z8 encore! xp ? f082a series product specification 222 opcode maps a description of the opcode map data and the abbreviations are provided in figure 30. figures 31 and 32 display the ez8 cpu instructions. table 129 lists opcode map abbrevi- ations. figure 30. opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps022827-1212 p r e l i m i n a r y opcode maps z8 encore! xp ? f082a series product specification 223 table 129. opcode map abbreviations abbreviation description abbreviation description b bit position. irr indirect register pair. cc condition code. p polarity (0 or 1). x 8-bit signed index or displacement. r 4-bit working register. da destination address. r 8-bit register. er extended addressing register. r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address. im immediate data value. r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address. ir indirect working register. ra relative. ir indirect register. rr working register pair. irr indirect working register pair. rr register pair.
ps022827-1212 p r e l i m i n a r y opcode maps z8 encore! xp ? f082a series product specification 224 figure 31. first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.1 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map 1
ps022827-1212 p r e l i m i n a r y opcode maps z8 encore! xp ? f082a series product specification 225 figure 32. second opcode map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) 3 , ldwx 5, 4 er2,er1
ps022827-1212 p r e l i m i n a r y electrical characteristics z8 encore! xp ? f082a series product specification 226 electrical characteristics the data in this chapter represents all known data prior to qualifi cation and characteriza- tion of the f082a series of products, and is therefore subjec t to change. additional electri- cal characteristics may be found in the individual chapters of this document. absolute maximum ratings stresses greater than those listed in table 13 0 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, tie unused in puts to one of the supply voltages (v dd or v ss ). table 130. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias ?40 +105 c storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 +5.5 v 1 ?0.3 +3.9 v 2 voltage on v dd pin with respect to v ss ?0.3 +3.6 v maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin ?25 +25 ma 8-pin packages maximum ratings at 0c to 70c total power dissipation 220 mw maximum current into v dd or out of v ss 60 ma 20-pin packages maximum ratings at 0c to 70c total power dissipation 430 mw
ps022827-1212 p r e l i m i n a r y dc characteristics z8 encore! xp ? f082a series product specification 227 dc characteristics table 131 lists the dc characteristics of the z8 encore! xp f082a series products. all voltages are referenced to v ss , the primary system ground. maximum current into v dd or out of v ss 120 ma 28-pin packages maximum ratings at 0c to 70c total power dissipation 450 mw maximum current into v dd or out of v ss 125 ma notes: operating temper ature is specified in dc characteristics. 1. this voltage applies to all pins except the following: v dd , av dd , pins supporting analog input (port b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1). on the 8-pin packages, this applies to all pins but v dd . 2. this voltage applies to pins on the 20-/28-pin packages supporting analog input (por t b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1). table 131. dc characteristics symbol parameter t a = ?40c to +105c (unless otherwise specified) units conditions minimum typical maximum v dd supply voltage 2.7 ? 3.6 v v il1 low level input voltage ?0.3 ? 0.3*v dd v v ih1 high level input voltage 0.7*v dd ? 5.5 v for all input pins without analog or oscillator function. for all sig- nal pins on the 8-pin devices. programmable pull-ups must also be disabled. v ih2 high level input voltage 0.7*v dd ?v dd +0.3 v for those pins with analog or oscillator function (20-/28-pin devices only), or when pro- grammable pull-ups are enabled. v ol1 low level output voltage ??0.4vi ol = 2 ma; v dd = 3.0 v ? high output drive disabled. notes: 1. this condition excludes all pins that have on-chip pull-ups, when driven low. 2. these values are provided for design guid ance only and are not tested in production. table 130. absolute maximum ratings (continued) parameter minimum maximum units notes
ps022827-1212 p r e l i m i n a r y dc characteristics z8 encore! xp ? f082a series product specification 228 v oh1 high level output voltage 2.4 ? ? v i oh = -2 ma; v dd = 3.0 v ? high output drive disabled. v ol2 low level output voltage ??0.6vi ol = 20 ma; v dd = 3.3 v ? high output drive enabled. v oh2 high level output voltage 2.4 ? ? v i oh = -20 ma; v dd = 3.3 v ? high output drive enabled. i ih input leakage cur- rent ?+ 0.002 + 5av in = v dd v dd = 3.3 v; i il input leakage cur- rent ?+ 0.007 + 5av in = v ss v dd = 3.3 v; i tl tristate leakage current ??+ 5a i led controlled current drive 1.8 3 4.5 ma {afs2,afs1} = {0,0} 2.8 7 10.5 ma {afs2,afs1} = {0,1} 7.8 13 19.5 ma {afs2,afs1} = {1,0} 12 20 30 ma {afs2,afs1} = {1,1} c pad gpio port pad capacitance ?8.0 2 ?pf c xin xin pad capaci- tance ?8.0 2 ?pf c xout x out pad capaci- tance ?9.5 2 ?pf i pu weak pull-up cur- rent 30 100 350 a v dd = 3.0 v?3.6 v v ram ram data reten- tion voltage tbd v voltage at which ram retains static values; no reading or writ- ing is allowed. table 131. dc characteristics (continued) symbol parameter t a = ?40c to +105c (unless otherwise specified) units conditions minimum typical maximum notes: 1. this condition excludes all pins that have on-chip pull-ups, when driven low. 2. these values are provided for design guid ance only and are not tested in production.
ps022827-1212 p r e l i m i n a r y dc characteristics z8 encore! xp ? f082a series product specification 229 table 132. power consumption symbol parameter v dd = 2.7 v to 3.6 v units conditions typical 1 maximum std temp 2 maximum ext temp 3 i dd stop supply current in stop mode 0.1 a no peripherals enabled. all pins driven to v dd or v ss . i dd halt supply current in halt mode (with all peripherals dis- abled) 35 55 65 a 32 khz. 520 a 5.5 mhz. 2.1 2.85 2.85 ma 20 mhz. i dd supply current in active mode (with all peripherals disabled) 2.8 ma 32 khz. 4.5 5.2 5.2 ma 5.5 mhz. 5.5 6.5 6.5 ma 10 mhz. 7.9 11.5 11.5 ma 20 mhz. i dd wdt watchdog timer supply current 0.9 1.0 1.1 a i dd xtal crystal oscillator supply current 40 a 32 khz. 230 a 4 mhz. 760 a 20 mhz. i dd ipo internal precision oscillator supply current 350 500 550 a i dd vbo voltage brown-out and low-voltage detect supply cur- rent 50 a for 20-/28-pin devices (vbo only); see note 4. for 8-pin devices; see note 4. i dd adc analog to digital converter supply current (with external refer- ence) 2.8 3.1 3.2 ma 32 khz. 3.1 3.6 3.7 ma 5.5 mhz. 3.3 3.7 3.8 ma 10 mhz. 3.7 4.2 4.3 ma 20 mhz. notes: 1. typical conditions are defined as v dd = 3.3 v and +30c. 2. standard temperature is defined as t a = 0c to +70c; these values not tested in production for worst case behavior, but are derived from product characte rization and provided for design guidance only. 3. extended temperature is defined as t a = ?40c to +105c; these values not tested in production for worst case behavior, but are derived from product characte rization and provided for design guidance only. 4. for this block to operate, the bandgap circuit is automa tically turned on and must be added to the total supply current. this bandgap current is only added once, regardless of how many peripherals are using it.
ps022827-1212 p r e l i m i n a r y dc characteristics z8 encore! xp ? f082a series product specification 230 i dd adcref adc internal ref- erence supply cur- rent 0 a see note 4. i dd cmp comparator sup- ply current 150 180 190 a see note 4. i dd lpo low-power opera- tional amplifier supply current 3 5 5 a driving a high-impedance load. i dd ts temperature sen- sor supply current 60 a see note 4. i dd bg band gap supply current 320 480 500 a for 20-/28-pin devices. for 8-pin devices. table 132. power consumption (continued) symbol parameter v dd = 2.7 v to 3.6 v units conditions typical 1 maximum std temp 2 maximum ext temp 3 notes: 1. typical conditions are defined as v dd = 3.3 v and +30c. 2. standard temperature is defined as t a = 0c to +70c; these values not tested in production for worst case behavior, but are derived from product characte rization and provided for design guidance only. 3. extended temperature is defined as t a = ?40c to +105c; these values not tested in production for worst case behavior, but are derived from product characte rization and provided for design guidance only. 4. for this block to operate, the bandgap circuit is automa tically turned on and must be added to the total supply current. this bandgap current is only added once, regardless of how many peripherals are using it.
ps022827-1212 p r e l i m i n a r y dc characteristics z8 encore! xp ? f082a series product specification 231 figure 33 displays the typical current cons umption while operating with all peripherals disabled, at 30 oc, versus the system clock frequency. figure 33. typical active mode i dd versus system clock frequency typical supply current - active mode 0 2 4 6 8 10 0 5 10 15 20 freq (mhz) idd (ma) vdd = 3.60v / 30c vdd = 3.30v / 30c vdd = 2.70v / 30c
ps022827-1212 p r e l i m i n a r y ac characteristics z8 encore! xp ? f082a series product specification 232 ac characteristics the section provides information about the ac characteristics and timing. all ac timing information assumes a standard load of 50 pf on all outputs. table 133. ac characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c (unless otherwise stated) units conditions minimum maximum f sysclk system clock frequency ? 20.0 mhz read-only from flash mem- ory 0.032768 20.0 mhz program or erasure of the flash memory f xtal crystal oscillator frequency ? 20. 0 mhz system clock frequencies below the crystal oscillator minimum require an exter- nal clock driver t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50 ns t xinl system clock low time 20 30 ns t clk = 50 ns t xinr system clock rise time ? 3 ns t clk = 50 ns t xinf system clock fall time ? 3 ns t clk = 50 ns table 134. internal precision osci llator electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c (unless otherwise stated) units conditions minimum typical maximum f ipo internal precision oscillator fre- quency (high speed) 5.53 mhz v dd = 3.3 v t a = 30c f ipo internal precision oscillator fre- quency (low speed) 32.7 khz v dd = 3.3 v t a = 30c f ipo internal precision oscillator error + 1+ 4% t ipost internal precision oscillator startup time 3s
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 233 on-chip peripheral ac and dc electrical characteristics table 135 tabulates the electrical characteristics of the por and vbo blocks. table 135. power-on reset and voltage brow n-out electrical characteristics and timing symbol parameter t a = ?40c to +105c units conditions minimum typical 1 maximum v por power-on reset voltage thresh- old 2.20 2.45 2.70 v v dd = v por v vbo voltage brown-out reset voltage threshold 2.15 2.40 2.65 v v dd = v vbo v por to v vbo hysteresis 50 75 mv starting v dd voltage to ensure valid power- on reset. ?v ss ?v t ana power-on reset analog delay ? 70 ? s v dd > v por ; t por digital reset delay follows t ana t por power-on reset digital delay 16 s 66 internal precision oscillator cycles + ipo startup time (t ipost ) t por power-on reset digital delay 1 ms 5000 internal precision oscillator cycles t smr stop mode recovery with crystal oscillator disabled 16 s 66 internal precision oscillator cycles t smr stop mode recovery with crystal oscillator enabled 1 ms 5000 internal precision oscillator cycles t vbo voltage brown-out pulse rejec- tion period ? 10 ? s period of time in which v dd < v vbo without generating a reset. note: data in the typical column is from characterization at 3.3 v and 30c. these values are provided for design guid- ance only and are not tested in production.
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 234 t ramp time for v dd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms t smp stop mode recovery pin pulse rejection period 20 ns for any smr pin or for the reset pin when it is asserted in stop mode. table 136. flash memory electr ical characteristics and timing parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c (unless otherwise stated) units notes minimum typical maximum flash byte read time 100 ? ? ns flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms writes to single address before next erase ??2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this parameter is only an issue when bypassing the flash controller. data retention 100 ? ? years 25c endurance 10,000 ? ? cycles program/erase cycles table 135. power-on reset and voltage brow n-out electrical characteristics and timing symbol parameter t a = ?40c to +105c units conditions minimum typical 1 maximum note: data in the typical column is from characterization at 3.3 v and 30c. these values are provided for design guid- ance only and are not tested in production.
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 235 table 137. watchdog timer electrical characteristics and timing symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c (unless otherwise stated) units conditions minimum typical maximum f wdt wdt oscillator frequency 10 khz f wdt wdt oscillator error + 50 % t wdtcal wdt calibrated time-out 0.98 1 1.02 s v dd = 3.3 v; t a = 30c 0.70 1 1.30 s v dd = 2.7 v to 3.6 v t a = 0c to 70c 0.50 1 1.50 s v dd = 2.7 v to 3.6 v t a = ?40c to +105c table 138. non-volatile data storage parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c units notes minimum typical maximum nvds byte read time 34 ? 519 s with system clock at 20 mhz nvds byte program time 0.171 ? 39. 7 ms with system clock at 20 mhz data retention 100 ? ? years 25c endurance 160,000 ? ? cycles cumulative write cycles for entire memory
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 236 table 139. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0 v to 3.6 v t a = 0c to +70c (unless otherwise stated) units conditions minimum typical maximum resolution 10 ? bits differential nonlinearity (dnl) ?1.0 ? 1.0 lsb 3 external v ref = 2.0 v; ? r s ? 3.0 k ? integral nonlineari ty (inl) ?3.0 ? 3.0 lsb 3 external v ref = 2.0 v; ? r s ? 3.0 k ? offset error with calibra- tion + 1l s b 3 absolute accuracy with calibration + 3l s b 3 v ref internal reference volt- age 1.0 2.0 1.1 2.2 1.2 2.4 v refsel=01 refsel=10 v ref internal reference varia- tion with temperature + 1.0 % temperature variation with v dd = 3.0 v ref internal reference volt- age variation with v dd + 0.5 % supply voltage varia- tion with t a = 30c r re- fout reference buffer output impedance 850 w when the internal ref- erence is buffered and driven out to the vref pin (refout = 1) single-shot conversion time ? 5129 ? sys- tem clock cycles all measurements but temperature sensor 10258 temperature sensor measurement notes: 1. analog source impedance affects the adc offset voltage (because of pin leakage) and input settling time. 2. devices are factory calibrated at v dd = 3.3 v and t a = +30c, so the adc is maximally accurate under these conditions. 3. lsbs are defined assuming 10-bit resolution. 4. this is the maximum recommended resistance seen by the adc input pin. 5. the input impedance is inversely proportional to the system clock frequency.
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 237 continuous conversion time ? 256 ? sys- tem clock cycles all measurements but temperature sensor 512 temperature sensor measurement signal input bandwidth ? 10 khz as defined by -3 db point r s analog source impedance 4 ??10k ? in unbuffered mode 500 k ? in buffered modes zin input impedance ? 150 k ? in unbuffered mode at 20 mhz 5 10 ? m ? in buffered modes vin input voltage range 0 v dd v unbuffered mode 0.3 v dd ?1.1 v buffered modes these values define the range over which the adc performs within spec; exceeding these values does not cause damage or insta- bility; see dc charac- teristics for absolute pin voltage limits. table 139. analog-to-digital converter electr ical characteristics and timing (continued) symbol parameter v dd = 3.0 v to 3.6 v t a = 0c to +70c (unless otherwise stated) units conditions minimum typical maximum notes: 1. analog source impedance affects the adc offset voltage (because of pin leakage) and input settling time. 2. devices are factory calibrated at v dd = 3.3 v and t a = +30c, so the adc is maximally accurate under these conditions. 3. lsbs are defined assuming 10-bit resolution. 4. this is the maximum recommended resistance seen by the adc input pin. 5. the input impedance is inversely proportional to the system clock frequency.
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 238 table 140. low power operational am plifier electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c units conditions minimum typical maximum av open loop voltage gain 80 db gbw gain/bandwidth product 500 khz pm phase margin 50 deg assuming 13 pf load capacitance. v oslpo input offset voltage + 1+ 4mv v oslpo input offset voltage (tem- perature drift) 110 ? v/c v in input voltage range 0.3 v dd ?1 v v out output voltage range 0.3 v dd ?1 v i out = 45 a. table 141. comparator electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = ?40c to +105c units conditions minimum typical maximum v os input dc offset 5 mv v cref programmable internal reference voltage + 5 % 20- and 28-pin devices. + 3 % 8-pin devices. t prop propagation delay 200 ns v hys input hysteresis 4 mv v in input voltage range v ss v dd ?1 v
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 239 table 142. temperature sensor electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v units conditions minimum typical maximum t aerr temperature error + 0.5 + 2 c over the range +20c to +30c (as mea- sured by adc). 1 + 1+ 5 c over the range +0c to +70c (as mea- sured by adc). + 2+ 7 c over the range +0c to +105c (as mea- sured by adc). + 7 c over the range ?40c to +105c (as mea- sured by adc). t wake wakeup time 80 100 ? s time required for tem- perature sensor to stabilize after enabling. note: devices are factory calibrated at for maximal accuracy between +20c and +30c, so the sensor is maximally accurate in that range. user recalibration for a diff erent temperature range is possible and increases accuracy near the new calibration point.
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 240 general purpose i/o port input data sample timing figure 34 displays timing of the gpio port input sampling. the input value on a gpio port pin is sampled on the rising edge of the system clock. the port value is available to the ez8 cpu on the second rising clock edge following the change of the port value. figure 34. port input sample timing table 143. gpio port input timing parameter abbreviation delay (ns) minimum maximum t s_port port input transition to x in rise setup time (not pictured) 5 ? t h_port x in rise to port input transition hold time (not pictured) 0 ? t smr gpio port pin pulse width to en sure stop mode recovery (for gpio port pins enabled as smr sources) 1 ? s system tclk port pin port value changes to 0 0 latched into port input input value port input data register latch clock data register port input data read on data bus port input data register value 0 read by ez8
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 241 general purpose i/o port output timing figure 35 and table 144 provide timin g information for gpio port pins. figure 35. gpio port output timing table 144. gpio port output timing parameter abbreviation delay (ns) minimum maximum gpio port pins t 1 x in rise to port output valid delay ? 15 t 2 x in rise to port output hold time 2 ? xin port output tclk t1 t2
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 242 on-chip debugger timing figure 36 and table 145 provide timing info rmation for the dbg pin. the dbg pin tim- ing specifications assume a 4 ns maximum rise and fall time. figure 36. on-chip debugger timing table 145. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 x in rise to dbg valid delay ? 15 t 2 x in rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 5 ? t 4 dbg to xin rise input hold time 5 ? xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 243 uart timing figure 37 and table 146 provide timing info rmation for uart pins for the case where cts is used for flow control. the cts to de assertion delay (t1) assumes the transmit data register has been loaded with data prior to cts assertion. figure 37. uart timing with cts table 146. uart timing with cts parameter abbreviation delay (ns) minimum maximum uart t 1 cts fall to de output delay 2 * x in period 2 * x in period + 1 bit time t 2 de assertion to txd falling edge (start bit) delay 5 t 3 end of stop bit(s) to de deassertion delay 5 cts de t1 (output) txd t2 (output) (input) start bit 0 bit 1 bit 7 parity stop end of stop bit(s) t3
ps022827-1212 p r e l i m i n a r y on-chip peripheral ac and dc electrical z8 encore! xp ? f082a series product specification 244 figure 38 and table 147 provide timing info rmation for uart pins for the case where cts is not used for flow cont rol. de asserts after the transmit data register has been written. de remains asserted for multiple characters as long as the transmit data register is written with the next character befo re the current character has completed. figure 38. uart timing without cts table 147. uart timing without cts parameter abbreviation delay (ns) minimum maximum uart t 1 de assertion to txd falling edge (start bit) delay 1 * x in period 1 bit time t 2 end of stop bit(s) to de deassertion delay (tx data register is empty) 5 de t1 (output) txd t2 (output) start bit0 bit 1 bit 7 parity stop end of stop bit(s)
ps022827-1212 p r e l i m i n a r y packaging z8 encore! xp ? f082a series product specification 245 packaging zilog?s product line of mcus includes th e z8f011a, z8f012a, z8f021a, z8f022a, z8f041a, z8f042a, z8f081a and z8f082a devices, which are available in the follow- ing packages: ? 8-pin plastic dual-inline package (pdip) ? 8-pin quad flat no-lead package (qfn)/mlf-s 1 ? 8-pin small outline integrated circuit package (soic) ? 20-pin small outline integrated circuit package (soic) ? 20-pin small shrink outline package (ssop) ? 20-pin plastic dual -inline package (pdip) ? 28-pin small outline integrated circuit package (soic) ? 28-pin small shrink outline package (ssop) ? 28-pin plastic dual -inline package (pdip) ? current diagrams for each of the se packages are published in zilog?s packaging product specification (ps0072) , which is available free for do wnload from the zilog website. 1. the footprint of the qfn)/mlf-s packag e is identical to that of the 8-pin so ic package, but with a lower profile.
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 246 ordering information order your f082a series products from zilog using the part numbers shown in table 148. for more information about ordering, please consult your local zilog sales office. the s ales location page on the zilog website lists all regional offices. table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description z8 encore! xp f082a series with 8 kb flas h, 10-bit analog-to-digital converter standard temperature: 0c to 70c z8f082apb020sg 8 kb 1 kb 0 6 14 2 4 1 1 1 pdip 8-pin package z8f082aqb020sg 8 kb 1 kb 0 6 14 2 4 1 1 1 qfn 8-pin package z8f082asb020sg 8 kb 1 kb 0 6 14 2 4 1 1 1 soic 8-pin package z8f082ash020sg 8 kb 1 kb 0 17 20 2 7 1 1 1 soic 20-pin package z8f082ahh020sg 8 kb 1 kb 0 17 20 2 7 1 1 1 ssop 20-pin package z8f082aph020sg 8 kb 1 kb 0 17 20 2 7 1 1 1 pdip 20-pin package z8f082asj020sg 8 kb 1 kb 0 23 20 2 8 1 1 1 soic 28-pin package z8f082ahj020sg 8 kb 1 kb 0 23 20 2 8 1 1 1 ssop 28-pin package z8f082apj020sg 8 kb 1 kb 0 23 20 2 8 1 1 1 pdip 28-pin package extended temperature: ?40c to 105c z8f082apb020eg 8 kb 1 kb 0 6 14 2 4 1 1 1 pdip 8-pin package z8f082aqb020eg 8 kb 1 kb 0 6 14 2 4 1 1 1 qfn 8-pin package z8f082asb020eg 8 kb 1 kb 0 6 14 2 4 1 1 1 soic 8-pin package z8f082ash020eg 8 kb 1 kb 0 17 20 2 7 1 1 1 soic 20-pin package z8f082ahh020eg 8 kb 1 kb 0 17 20 2 7 1 1 1 ssop 20-pin package z8f082aph020eg 8 kb 1 kb 0 17 20 2 7 1 1 1 pdip 20-pin package z8f082asj020eg 8 kb 1 kb 0 23 20 2 8 1 1 1 soic 28-pin package z8f082ahj020eg 8 kb 1 kb 0 23 20 2 8 1 1 1 ssop 28-pin package z8f082apj020eg 8 kb 1 kb 0 23 20 2 8 1 1 1 pdip 28-pin package
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 247 z8 encore! xp f082a series with 8 kb flash standard temperature: 0c to 70c z8f081apb020sg 8 kb 1 kb 0 6 13 2 0 1 1 0 pdip 8-pin package z8f081aqb020sg 8 kb 1 kb 0 6 13 2 0 1 1 0 qfn 8-pin package z8f081asb020sg 8 kb 1 kb 0 6 13 2 0 1 1 0 soic 8-pin package z8f081ash020sg 8 kb 1 kb 0 17 19 2 0 1 1 0 soic 20-pin package z8f081ahh020sg 8 kb 1 kb 0 17 19 2 0 1 1 0 ssop 20-pin package z8f081aph020sg 8 kb 1 kb 0 17 19 2 0 1 1 0 pdip 20-pin package z8f081asj020sg 8 kb 1 kb 0 25 19 2 0 1 1 0 soic 28-pin package z8f081ahj020sg 8 kb 1 kb 0 25 19 2 0 1 1 0 ssop 28-pin package z8f081apj020sg 8 kb 1 kb 0 25 19 2 0 1 1 0 pdip 28-pin package extended temperature: ?40c to 105c z8f081apb020eg 8 kb 1 kb 0 6 13 2 0 1 1 0 pdip 8-pin package z8f081aqb020eg 8 kb 1 kb 0 6 13 2 0 1 1 0 qfn 8-pin package z8f081asb020eg 8 kb 1 kb 0 6 13 2 0 1 1 0 soic 8-pin package z8f081ash020eg 8 kb 1 kb 0 17 19 2 0 1 1 0 soic 20-pin package z8f081ahh020eg 8 kb 1 kb 0 17 19 2 0 1 1 0 ssop 20-pin package z8f081aph020eg 8 kb 1 kb 0 17 19 2 0 1 1 0 pdip 20-pin package z8f081asj020eg 8 kb 1 kb 0 25 19 2 0 1 1 0 soic 28-pin package z8f081ahj020eg 8 kb 1 kb 0 25 19 2 0 1 1 0 ssop 28-pin package z8f081apj020eg 8 kb 1 kb 0 25 19 2 0 1 1 0 pdip 28-pin package table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 248 z8 encore! xp f082a series with 4 kb fl ash, 10-bit analog-to-digital converter standard temperature: 0c to 70c z8f042apb020sg 4 kb 1 kb 128 b 6 14 2 4 1 1 1 pdip 8-pin package z8f042aqb020sg 4 kb 1 kb 128 b 6 14 2 4 1 1 1 qfn 8-pin package z8f042asb020sg 4 kb 1 kb 128 b 6 14 2 4 1 1 1 soic 8-pin package z8f042ash020sg 4 kb 1 kb 128 b 17 20 2 7 1 1 1 soic 20-pin package z8f042ahh020sg 4 kb 1 kb 128 b 17 20 2 7 1 1 1 ssop 20-pin package z8f042aph020sg 4 kb 1 kb 128 b 17 20 2 7 1 1 1 pdip 20-pin package z8f042asj020sg 4 kb 1 kb 128 b 23 20 2 8 1 1 1 soic 28-pin package z8f042ahj020sg 4 kb 1 kb 128 b 23 20 2 8 1 1 1 ssop 28-pin package z8f042apj020sg 4 kb 1 kb 128 b 23 20 2 8 1 1 1 pdip 28-pin package extended temperature: ?40c to 105c z8f042apb020eg 4 kb 1 kb 128 b 6 14 2 4 1 1 1 pdip 8-pin package z8f042aqb020eg 4 kb 1 kb 128 b 6 14 2 4 1 1 1 qfn 8-pin package z8f042asb020eg 4 kb 1 kb 128 b 6 14 2 4 1 1 1 soic 8-pin package z8f042ash020eg 4 kb 1 kb 128 b 17 20 2 7 1 1 1 soic 20-pin package z8f042ahh020eg 4 kb 1 kb 128 b 17 20 2 7 1 1 1 ssop 20-pin package z8f042aph020eg 4 kb 1 kb 128 b 17 20 2 7 1 1 1 pdip 20-pin package z8f042asj020eg 4 kb 1 kb 128 b 23 20 2 8 1 1 1 soic 28-pin package z8f042ahj020eg 4 kb 1 kb 128 b 23 20 2 8 1 1 1 ssop 28-pin package z8f042apj020eg 4 kb 1 kb 128 b 23 20 2 8 1 1 1 pdip 28-pin package table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 249 z8 encore! xp f082a series with 4 kb flash standard temperature: 0c to 70c z8f041apb020sg 4 kb 1 kb 128 b 6 13 2 0 1 1 0 pdip 8-pin package z8f041aqb020sg 4 kb 1 kb 128 b 6 13 2 0 1 1 0 qfn 8-pin package z8f041asb020sg 4 kb 1 kb 128 b 6 13 2 0 1 1 0 soic 8-pin package z8f041ash020sg 4 kb 1 kb 128 b 17 19 2 0 1 1 0 soic 20-pin package z8f041ahh020sg 4 kb 1 kb 128 b 17 19 2 0 1 1 0 ssop 20-pin package z8f041aph020sg 4 kb 1 kb 128 b 17 19 2 0 1 1 0 pdip 20-pin package z8f041asj020sg 4 kb 1 kb 128 b 25 19 2 0 1 1 0 soic 28-pin package z8f041ahj020sg 4 kb 1 kb 128 b 25 19 2 0 1 1 0 ssop 28-pin package z8f041apj020sg 4 kb 1 kb 128 b 25 19 2 0 1 1 0 pdip 28-pin package extended temperature: ?40c to 105c z8f041apb020eg 4 kb 1 kb 128 b 6 13 2 0 1 1 0 pdip 8-pin package z8f041aqb020eg 4 kb 1 kb 128 b 6 13 2 0 1 1 0 qfn 8-pin package z8f041asb020eg 4 kb 1 kb 128 b 6 13 2 0 1 1 0 soic 8-pin package z8f041ash020eg 4 kb 1 kb 128 b 17 19 2 0 1 1 0 soic 20-pin package z8f041ahh020eg 4 kb 1 kb 128 b 17 19 2 0 1 1 0 ssop 20-pin package z8f041aph020eg 4 kb 1 kb 128 b 17 19 2 0 1 1 0 pdip 20-pin package z8f041asj020eg 4 kb 1 kb 128 b 25 19 2 0 1 1 0 soic 28-pin package z8f041ahj020eg 4 kb 1 kb 128 b 25 19 2 0 1 1 0 ssop 28-pin package z8f041apj020eg 4 kb 1 kb 128 b 25 19 2 0 1 1 0 pdip 28-pin package table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 250 z8 encore! xp f082a series with 2 kb fl ash, 10-bit analog-to-digital converter standard temperature: 0c to 70c z8f022apb020sg 2 kb 512 b 64 b 6 14 2 4 1 1 1 pdip 8-pin package z8f022aqb020sg 2 kb 512 b 64 b 6 14 2 4 1 1 1 qfn 8-pin package z8f022asb020sg 2 kb 512 b 64 b 6 14 2 4 1 1 1 soic 8-pin package z8f022ash020sg 2 kb 512 b 64 b 17 20 2 7 1 1 1 soic 20-pin package z8f022ahh020sg 2 kb 512 b 64 b 17 20 2 7 1 1 1 ssop 20-pin package z8f022aph020sg 2 kb 512 b 64 b 17 20 2 7 1 1 1 pdip 20-pin package z8f022asj020sg 2 kb 512 b 64 b 23 20 2 8 1 1 1 soic 28-pin package z8f022ahj020sg 2 kb 512 b 64 b 23 20 2 8 1 1 1 ssop 28-pin package z8f022apj020sg 2 kb 512 b 64 b 23 20 2 8 1 1 1 pdip 28-pin package extended temperature: ?40c to 105c z8f022apb020eg 2 kb 512 b 64 b 6 14 2 4 1 1 1 pdip 8-pin package z8f022aqb020eg 2 kb 512 b 64 b 6 14 2 4 1 1 1 qfn 8-pin package z8f022asb020eg 2 kb 512 b 64 b 6 14 2 4 1 1 1 soic 8-pin package z8f022ash020eg 2 kb 512 b 64 b 17 20 2 7 1 1 1 soic 20-pin package z8f022ahh020eg 2 kb 512 b 64 b 17 20 2 7 1 1 1 ssop 20-pin package z8f022aph020eg 2 kb 512 b 64 b 17 20 2 7 1 1 1 pdip 20-pin package z8f022asj020eg 2 kb 512 b 64 b 23 20 2 8 1 1 1 soic 28-pin package z8f022ahj020eg 2 kb 512 b 64 b 23 20 2 8 1 1 1 ssop 28-pin package z8f022apj020eg 2 kb 512 b 64 b 23 20 2 8 1 1 1 pdip 28-pin package table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 251 z8 encore! xp f082a series with 2 kb flash standard temperature: 0c to 70c z8f021apb020sg 2 kb 512 b 64 b 6 13 2 0 1 1 0 pdip 8-pin package z8f021aqb020sg 2 kb 512 b 64 b 6 13 2 0 1 1 0 qfn 8-pin package z8f021asb020sg 2 kb 512 b 64 b 6 13 2 0 1 1 0 soic 8-pin package z8f021ash020sg 2 kb 512 b 64 b 17 19 2 0 1 1 0 soic 20-pin package z8f021ahh020sg 2 kb 512 b 64 b 17 19 2 0 1 1 0 ssop 20-pin package z8f021aph020sg 2 kb 512 b 64 b 17 19 2 0 1 1 0 pdip 20-pin package z8f021asj020sg 2 kb 512 b 64 b 25 19 2 0 1 1 0 soic 28-pin package z8f021ahj020sg 2 kb 512 b 64 b 25 19 2 0 1 1 0 ssop 28-pin package z8f021apj020sg 2 kb 512 b 64 b 25 19 2 0 1 1 0 pdip 28-pin package extended temperature: ?40c to 105c z8f021apb020eg 2 kb 512 b 64 b 6 13 2 0 1 1 0 pdip 8-pin package z8f021aqb020eg 2 kb 512 b 64 b 6 13 2 0 1 1 0 qfn 8-pin package z8f021asb020eg 2 kb 512 b 64 b 6 13 2 0 1 1 0 soic 8-pin package z8f021ash020eg 2 kb 512 b 64 b 17 19 2 0 1 1 0 soic 20-pin package z8f021ahh020eg 2 kb 512 b 64 b 17 19 2 0 1 1 0 ssop 20-pin package z8f021aph020eg 2 kb 512 b 64 b 17 19 2 0 1 1 0 pdip 20-pin package z8f021asj020eg 2 kb 512 b 64 b 25 19 2 0 1 1 0 soic 28-pin package z8f021ahj020eg 2 kb 512 b 64 b 25 19 2 0 1 1 0 ssop 28-pin package z8f021apj020eg 2 kb 512 b 64 b 25 19 2 0 1 1 0 pdip 28-pin package table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 252 z8 encore! xp f082a series with 1 kb flas h, 10-bit analog-to-digital converter standard temperature: 0c to 70c z8f012apb020sg 1 kb 256 b 16 b 6 14 2 4 1 1 1 pdip 8-pin package z8f012aqb020sg 1 kb 256 b 16 b 6 14 2 4 1 1 1 qfn 8-pin package z8f012asb020sg 1 kb 256 b 16 b 6 14 2 4 1 1 1 soic 8-pin package z8f012ash020sg 1 kb 256 b 16 b 17 20 2 7 1 1 1 soic 20-pin package z8f012ahh020sg 1 kb 256 b 16 b 17 20 2 7 1 1 1 ssop 20-pin package z8f012aph020sg 1 kb 256 b 16 b 17 20 2 7 1 1 1 pdip 20-pin package z8f012asj020sg 1 kb 256 b 16 b 23 20 2 8 1 1 1 soic 28-pin package z8f012ahj020sg 1 kb 256 b 16 b 23 20 2 8 1 1 1 ssop 28-pin package z8f012apj020sg 1 kb 256 b 16 b 23 20 2 8 1 1 1 pdip 28-pin package extended temperature: ?40c to 105c z8f012apb020eg 1 kb 256 b 16 b 6 14 2 4 1 1 1 pdip 8-pin package z8f012aqb020eg 1 kb 256 b 16 b 6 14 2 4 1 1 1 qfn 8-pin package z8f012asb020eg 1 kb 256 b 16 b 6 14 2 4 1 1 1 soic 8-pin package z8f012ash020eg 1 kb 256 b 16 b 17 20 2 7 1 1 1 soic 20-pin package z8f012ahh020eg 1 kb 256 b 16 b 17 20 2 7 1 1 1 ssop 20-pin package z8f012aph020eg 1 kb 256 b 16 b 17 20 2 7 1 1 1 pdip 20-pin package z8f012asj020eg 1 kb 256 b 16 b 23 20 2 8 1 1 1 soic 28-pin package z8f012ahj020eg 1 kb 256 b 16 b 23 20 2 8 1 1 1 ssop 28-pin package z8f012apj020eg 1 kb 256 b 16 b 23 20 2 8 1 1 1 pdip 28-pin package table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 253 z8 encore! xp f082a series with 1 kb flash standard temperature: 0c to 70c z8f011apb020sg 1 kb 256 b 16 b 6 13 2 0 1 1 0 pdip 8-pin package z8f011aqb020sg 1 kb 256 b 16 b 6 13 2 0 1 1 0 qfn 8-pin package z8f011asb020sg 1 kb 256 b 16 b 6 13 2 0 1 1 0 soic 8-pin package z8f011ash020sg 1 kb 256 b 16 b 17 19 2 0 1 1 0 soic 20-pin package z8f011ahh020sg 1 kb 256 b 16 b 17 19 2 0 1 1 0 ssop 20-pin package z8f011aph020sg 1 kb 256 b 16 b 17 19 2 0 1 1 0 pdip 20-pin package z8f011asj020sg 1 kb 256 b 16 b 25 19 2 0 1 1 0 soic 28-pin package z8f011ahj020sg 1 kb 256 b 16 b 25 19 2 0 1 1 0 ssop 28-pin package z8f011apj020sg 1 kb 256 b 16 b 25 19 2 0 1 1 0 pdip 28-pin package extended temperature: ?40c to 105c z8f011apb020eg 1 kb 256 b 16 b 6 13 2 0 1 1 0 pdip 8-pin package z8f011aqb020eg 1 kb 256 b 16 b 6 13 2 0 1 1 0 qfn 8-pin package z8f011asb020eg 1 kb 256 b 16 b 6 13 2 0 1 1 0 soic 8-pin package z8f011ash020eg 1 kb 256 b 16 b 17 19 2 0 1 1 0 soic 20-pin package z8f011ahh020eg 1 kb 256 b 16 b 17 19 2 0 1 1 0 ssop 20-pin package z8f011aph020eg 1 kb 256 b 16 b 17 19 2 0 1 1 0 pdip 20-pin package z8f011asj020eg 1 kb 256 b 16 b 25 19 2 0 1 1 0 soic 28-pin package z8f011ahj020eg 1 kb 256 b 16 b 25 19 2 0 1 1 0 ssop 28-pin package z8f011apj020eg 1 kb 256 b 16 b 25 19 2 0 1 1 0 pdip 28-pin package table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 254 z8 encore! xp f082a series development kit z8f08a28100kitg z8 encore! xp f082a series 28-pin development kit z8f04a28100kitg z8 encore! xp f042a series 28-pin development kit z8f04a08100kitg z8 encore! xp f042a series 8-pin development kit ZUSBSC00100ZACG usb smart cable accessory kit zusboptsc01zacg usb opto-isolate d smart cable accessory kit zenetsc0100zacg ethernet smart cable accessory kit table 148. z8 encore! xp f082a series ordering matrix part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022827-1212 p r e l i m i n a r y ordering information z8 encore! xp ? f082a series product specification 255 part number su ffix designations zilog part numbers consist of a number of components, as indicated in the following example. example. part number z8f042ash020sg is an 8-bit flash mcu with 4 kb of program memory, equipped with advanced analog peripherals in a 20-pin soic package, operating within a 0oc to +70oc temperature ra nge and built using lead-free solder. z8 f 04 2a s h 020 s g environmental flow ? g = green plastic packaging compound temperature range s = standard, 0c to 70c ? e = extended, ?40c to +105c speed ? 020 = 20 mhz pin count ? b = 8 h = 20 ? j = 28 package h = ssop p = pdip q = qfn ? s = soic device type 2a = contains advanced analog peripherals 1a = does not contain advanced analog peripherals memory size? 08 = 8 kb flash, 1 kb ram, 0 b nvds 04 = 4 kb flash, 1 kb ram, 128 b nvds ? 02 = 2 kb flash, 512 b ram, 64 b nvds 01 = 1 kb flash, 256 b ram, 16 b nvds memory type ? f = flash device family z8 = zilog?s 8-bit microcontroller
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 256 index numerics 10-bit adc 6 a absolute maximum ratings 226 ac characteristics 232 adc 208 architecture 124 block diagram 125 continuous conversion 127 control register 134, 135 control register definitions 133 data high byte register 136 data low bits register 137 electrical characteristics and timing 236 operation 125 single-shot conversion 126 adcctl register 134, 135 adcdh register 136 adcdl register 137 adcx 208 add 208 add - extended addressing 208 add with carry 208 add with carry - extended addressing 208 additional symbols 207 address space 15 addx 208 analog signals 11 analog-to-digital co nverter (adc) 124 and 210 andx 210 arithmetic instructions 208 assembly language programming 204 assembly language syntax 205 b b 207 b 206 baud rate generator, uart 110 bclr 209 binary number suffix 207 bit 209 bit 206 clear 209 manipulation instructions 209 set 209 set or clear 209 swap 209 test and jump 211 test and jump if non-zero 211 test and jump if zero 211 bit jump and test if non-zero 211 bit swap 211 block diagram 3 block transfer instructions 209 brk 211 bset 209 bswap 209, 211 btj 211 btjnz 211 btjz 211 c call procedure 211 capture mode 87, 88 capture/compare mode 88 cc 206 ccf 209 characteristics, electrical 226 clear 210 clr 210 com 210 compare 87 compare - extended addressing 208 compare mode 87 compare with carry 208
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 257 compare with carry - ex tended addressing 208 complement 210 complement carry flag 209 condition code 206 continuous conversion (adc) 127 continuous mode 87 control register definition, uart 110 control registers 15, 18 counter modes 87 cp 208 cpc 208 cpcx 208 cpu and peripheral overview 4 cpu control instructions 209 cpx 208 customer feedback form 265 d da 206, 208 data memory 17 dc characteristics 227 debugger, on-chip 180 dec 208 decimal adjust 208 decrement 208 decrement and jump non-zero 211 decrement word 208 decw 208 destination operand 207 device, port availability 36 di 209 direct address 206 disable interrupts 209 djnz 211 dst 207 e ei 209 electrical characteristics 226 adc 236 flash memory and timing 234 gpio input data sample timing 240 watchdog timer 235, 238 enable interrupt 209 er 206 extended addressing register 206 external pin reset 26 ez8 cpu features 4 ez8 cpu instruction classes 207 ez8 cpu instruction notation 206 ez8 cpu instruction set 204 ez8 cpu instruction summary 212 f fctl register 155, 161, 162 features, z8 encore! 1 first opcode map 224 flags 207 flags register 207 flash controller 6 option bit address space 162 option bit configuration - reset 159 program memory address 0000h 162 program memory address 0001h 164 flash memory 146 arrangement 147 byte programming 151 code protection 149 configurations 146 control register definitions 153, 161 controller bypass 152 electrical characteristics and timing 234 flash control register 155, 161, 162 flash option bits 150 flash status register 155 flow chart 148 frequency high and low byte registers 157 mass erase 152 operation 147 operation timing 149 page erase 152 page select register 156, 157 fps register 156, 157 fstat register 155
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 258 g gated mode 88 general-purpose i/o 36 gpio 6, 36 alternate functions 37 architecture 37 control register definitions 44 input data sample timing 240 interrupts 44 port a-c pull-up enable sub-registers 50, 51 port a-h address registers 45 port a-h alternate fu nction sub-registers 47 port a-h control registers 46 port a-h data direction sub-registers 46 port a-h high drive enable sub-registers 48 port a-h input data registers 52 port a-h output control sub-registers 47 port a-h output data registers 52, 53 port a-h stop mode re covery sub-registers 49 port availability by device 36 port input timing 240 port output timing 241 h h 207 halt 209 halt mode 33, 209 hexadecimal number prefix/suffix 207 i i2c 6 im 206 immediate data 206 immediate operand prefix 207 inc 208 increment 208 increment word 208 incw 208 indexed 207 indirect address prefix 207 indirect register 206 indirect register pair 206 indirect working register 206 indirect working register pair 206 infrared encoder/decoder (irda) 120 instruction set 204 instruction set, ez8 cpu 204 instructions adc 208 adcx 208 add 208 addx 208 and 210 andx 210 arithmetic 208 bclr 209 bit 209 bit manipulation 209 block transfer 209 brk 211 bset 209 bswap 209, 211 btj 211 btjnz 211 btjz 211 call 211 ccf 209 clr 210 com 210 cp 208 cpc 208 cpcx 208 cpu control 209 cpx 208 da 208 dec 208 decw 208 di 209 djnz 211 ei 209 halt 209 inc 208 incw 208 iret 211 jp 211
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 259 ld 210 ldc 210 ldci 209, 210 lde 210 ldei 209 ldx 210 lea 210 logical 210 mult 208 nop 209 or 210 orx 210 pop 210 popx 210 program control 211 push 210 pushx 210 rcf 209, 210 ret 211 rl 211 rlc 211 rotate and shift 211 rr 211 rrc 211 sbc 208 scf 209, 210 sra 211 srl 211 srp 210 stop 210 sub 208 subx 208 swap 211 tcm 209 tcmx 209 tm 209 tmx 209 trap 211 watchdog timer refresh 210 xor 210 xorx 210 instructions, ez8 classes of 207 interrupt control register 69 interrupt controller 55 architecture 55 interrupt assertion types 58 interrupt vectors and priority 58 operation 57 register definitions 60 software interrupt assertion 59 interrupt edge select register 67 interrupt request 0 register 60 interrupt request 1 register 61 interrupt request 2 register 62 interrupt return 211 interrupt vector listing 55 interrupts uart 108 ir 206 ir 206 irda architecture 120 block diagram 120 control register definitions 123 operation 120 receiving data 122 transmitting data 121 iret 211 irq0 enable high and low bit registers 62 irq1 enable high and low bit registers 64 irq2 enable high and low bit registers 65 irr 206 irr 206 j jp 211 jump, conditional, relative, and relative conditional 211 l ld 210 ldc 210 ldci 209, 210 lde 210 ldei 209, 210 ldx 210
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 260 lea 210 load 210 load constant 209 load constant to/fro m program memory 210 load constant with auto-increment addresses 210 load effective address 210 load external data 210 load external data to/fro m data memory and auto- increment addresses 209 load external to/from data memory and auto-incre- ment addresses 210 load using extended addressing 210 logical and 210 logical and/extended addressing 210 logical exclusive or 210 logical exclusive or/extended addressing 210 logical instructions 210 logical or 210 logical or/extended addressing 210 low power modes 32 m master interrupt enable 57 memory data 17 program 15 mode capture 87, 88 capture/compare 88 continuous 87 counter 87 gated 88 one-shot 87 pwm 87, 88 modes 87 mult 208 multiply 208 multiprocessor mode, uart 105 n nop (no operation) 209 notation b 206 cc 206 da 206 er 206 im 206 ir 206 ir 206 irr 206 irr 206 p 206 r 206 r 206 ra 206 rr 206 rr 206 vector 207 x 207 notational shorthand 206 o ocd architecture 180 auto-baud detector/generator 183 baud rate limits 184 block diagram 180 breakpoints 185 commands 186 control register 191 data format 183 dbg pin to rs-232 interface 181 debug mode 182 debugger break 211 interface 181 serial errors 184 status register 192 timing 242 ocd commands execute instruction (12h) 190 read data memory (0dh) 190 read ocd control re gister (05h) 188 read ocd revision (00h) 187 read ocd status register (02h) 187 read program counter (07h) 188
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 261 read program memory (0bh) 189 read program memory crc (0eh) 190 read register (09h) 189 read runtime counter (03h) 187 step instruction (10h) 190 stuff instruction (11h) 190 write data memory (0ch) 189 write ocd control register (04h) 188 write program counter (06h) 188 write program memory (0ah) 189 write register (08h) 188 on-chip debugger (ocd) 180 on-chip debugger signals 11 on-chip oscillator 198 one-shot mode 87 opcode map abbreviations 223 cell description 222 first 224 second after 1fh 225 operational description 22, 32, 36, 55, 70, 93, 99, 120, 124, 139, 140, 144, 146, 159, 176, 180, 193, 198, 203 or 210 ordering information 246 orx 210 oscillator signals 11 p p 206 packaging 245 part selection guide 2 pc 207 peripheral ac and dc electrical characteristics 233 pin characteristics 12 pin descriptions 8 polarity 206 pop 210 pop using extended addressing 210 popx 210 port availability, device 36 port input timing (gpio) 240 port output timing, gpio 241 power supply signals 12 power-on and voltage brownout electrical charac- teristics and timing 233 power-on reset (por) 24 program control instructions 211 program counter 207 program memory 15 push 210 push using extended addressing 210 pushx 210 pwm mode 87, 88 pxaddr register 45 pxctl register 46 r r 206 r 206 ra register address 206 rcf 209, 210 receive irda data 122 receiving uart data-inte rrupt-driven method 104 receiving uart data-polled method 103 register 206 adc control (adcctl) 134, 135 adc data high byte (adcdh) 136 adc data low bits (adcdl) 137 flash control (fctl) 155, 161, 162 flash high and low byte (ffreqh and fre- eql) 157 flash page select (fps) 156, 157 flash status (fstat) 155 gpio port a-h address (pxaddr) 45 gpio port a-h alternate function sub-registers 47 gpio port a-h control address (pxctl) 46 gpio port a-h data direction sub-registers 46 ocd control 191 ocd status 192 uartx baud rate high byte (uxbrh) 117 uartx baud rate lo w byte (uxbrl) 117 uartx control 0 (uxctl0) 111, 117
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 262 uartx control 1 (uxctl1) 112 uartx receive data (uxrxd) 116 uartx status 0 (uxstat0) 114 uartx status 1 (uxstat1) 115 uartx transmit data (uxtxd) 116 watchdog timer control (wdtctl) 30, 96, 141, 196 watchdog timer reload high byte (wdth) 97 watchdog timer reload low byte (wdtl) 98 watchdog timer reload upper byte (wdtu) 97 register file 15 register pair 206 register pointer 207 reset and stop mode characteristics 23 and stop mode recovery 22 carry flag 209 sources 24 ret 211 return 211 rl 211 rlc 211 rotate and shift instuctions 211 rotate left 211 rotate left through carry 211 rotate right 211 rotate right th rough carry 211 rp 207 rr 206, 211 rr 206 rrc 211 s sbc 208 scf 209, 210 second opcode map after 1fh 225 set carry flag 209, 210 set register pointer 210 shift right arithmatic 211 shift right logical 211 signal descriptions 10 single-shot conversion (adc) 126 software trap 211 source operand 207 sp 207 sra 211 src 207 srl 211 srp 210 stack pointer 207 stop 210 stop mode 32 stop mode 210 stop mode recovery sources 27 using a gpio port pin transition 28 using watchdog timer time-out 28 stop mode recovery sources 29 using a gpio port pin transition 29 sub 208 subtract 208 subtract - extended addressing 208 subtract with carry 208 subtract with carry - extended addressing 208 subx 208 swap 211 swap nibbles 211 symbols, additional 207 t tcm 209 tcmx 209 test complement under mask 209 test complement under mask - extended addressing 209 test under mask 209 test under mask - extended addressing 209 timer signals 10 timers 70 architecture 70 block diagram 71 capture mode 79, 80, 87, 88 capture/compare mode 83, 88 compare mode 81, 87
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 263 continuous mode 72, 87 counter mode 73, 74 counter modes 87 gated mode 82, 88 one-shot mode 71, 87 operating mode 71 pwm mode 76, 77, 87, 88 reading the timer count values 84 reload high and low byte registers 91 timer control register definitions 85 timer output signal operation 84 timers 0-3 control registers 85, 86 high and low byte registers 89, 92 tm 209 tmx 209 transmit irda data 121 transmitting uart data-polled method 101 transmitting uart dat-interrupt-driven method 102 trap 211 u uart 6 architecture 99 baud rate generator 110 baud rates table 118 control register definitions 110 controller signals 10 interrupts 108 multiprocessor mode 105 receiving data using in terrupt-driven method 104 receiving data using the polled method 103 transmitting data usin the interrupt-driven method 102 transmitting data using the polled method 101 x baud rate high and low registers 117 x control 0 and control 1 registers 110 x status 0 and status 1 registers 114, 115 uxbrh register 117 uxbrl register 117 uxctl0 register 111, 117 uxctl1 register 112 uxrxd register 116 uxstat0 register 114 uxstat1 register 115 uxtxd register 116 v vector 207 voltage brownout reset (vbr) 25 w watchdog timer approximate time-out delay 93 approximate time-out delays 140 cntl 25 control register 96 electrical characteristics and timing 235, 238 interrupt in normal operation 94 interrupt in stop mode 94 operation 140 refresh 94, 210 reload unlock sequence 95 reload upper, high and low registers 97 reset 26 reset in normal operation 95 reset in stop mode 95 time-out response 94 wdtctl register 30, 96, 141, 196 wdth register 97 wdtl register 98 working register 206 working register pair 206 wtdu register 97 x x 207 xor 210 xorx 210
ps022827-1212 p r e l i m i n a r y index z8 encore! xp ? f082a series product specification 264 z z8 encore! block diagram 3 features 1 part selection guide 2
ps022827-1212 p r e l i m i n a r y customer support z8 encore! xp ? f082a series product specification 265 customer support to share comments, get your technical questio ns answered, or report issues you may be experiencing with our products, please visit zilog?s technical support page at ? http://support.zilog.com . to learn more about this produc t, find additional documentati on, or to discover other fac- ets about zilog product offerings, pl ease visit the zilog knowledge base at http:// zilog.com/kb or consider participating in the zilog forum at http://zilog.com/forum . this publication is subject to replacement by a later edition. to determine whether a later edition exists, please vis it the zilog website at http://www.zilog.com .

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